Senior Digital Design Engineer - Timing & Synthesis

Infineon Technologies; Singapore; On-site; SGD 90,000 - 120,000; Full time

Job summary

Infineon Technologies in Singapore is seeking a Digital Design Engineer to join the R&D team. You will perform RTL-to-gate synthesis, run STA, and collaborate with design, verification, and PD teams to ensure timing closure and optimization.

The role emphasizes developing and maintaining synthesis scripts, analyzing timing issues, and reporting results. Strong scripting skills and experience with ICC2/Innovus are valued, along with a degree in EE/CE and 3–5+ years in hardware.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 3–5+ years hardware engineering experience.
• Hands-on experience with logic synthesis, LEC, STA, timing constraints, and timing convergence.
• Experience with ECOs, crosstalk and noise analysis, and PD basics like floorplanning and placement using ICC2 or Innovus.

Responsibilities

• Perform RTL-to-gate synthesis using EDA tools to generate optimized gate-level netlists.
• Run Static Timing Analysis (STA) including setup/hold checks across pre- and post-layout stages.
• Collaborate with design, verification, and PD teams to ensure timing closure and optimization.
• Assist in development and maintenance of synthesis and STA scripts and methodologies.
• Analyze and resolve timing issues with cross-functional teams.
• Run timing constraint checks and logic equivalency checks (LEC).
• Participate in design reviews and provide feedback on timing and synthesis aspects.
• Document and report synthesis and STA results, highlighting key findings and recommendations.

Skills

Hardware engineering

Scripting (Python, Tcl, Perl)

Timing closure

Cross-functional collaboration

Education

Bachelor’s/Master’s degree in Electrical Engineering or Computer Engineering

Tools

Synopsys Design Compiler

Cadence Genus

Synopsys PrimeTime

Cadence Tempus

ICC2

Innovus

Job description

Infineon Technologies in Singapore is seeking a Digital Design Engineer to join the R&D team. You will perform RTL-to-gate synthesis, run STA, and collaborate with design, verification, and PD teams to ensure timing closure and optimization.

The role emphasizes developing and maintaining synthesis scripts, analyzing timing issues, and reporting results. Strong scripting skills and experience with ICC2/Innovus are valued, along with a degree in EE/CE and 3–5+ years in hardware.