Senior Analog IC Design Engineer — High-Performance CMOS

Darwin Recruitment; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Darwin Recruitment is seeking a Staff / Senior Staff Analog IC Design Engineer to drive the development of high‑performance analog/mixed‑signal ICs for advanced semiconductor applications. The role involves circuit design, verification, and collaboration with cross‑functional teams to deliver robust IP for SoCs.

Responsibilities include schematic design, SPICE simulations, layout coordination, and post‑silicon validation, with opportunities to explore cryogenic environments where applicable.

Qualifications

• Master’s or PhD in Electrical Engineering or closely related discipline.
• Strong understanding of semiconductor device physics and CMOS technologies.
• Proven analog IC design experience with blocks like LDOs, Op-amps, PLLs, ADCs/DACs.

Responsibilities

• Design high-performance analog/mixed-signal ICs (amplifiers, data converters, regulators).
• Develop custom analog circuits to meet noise, gain, bandwidth, and linearity requirements.
• Perform schematic design and SPICE simulations across PVT corners.
• Collaborate with layout, digital, system teams to integrate analog IP into SoCs.
• Conduct design reviews and improve methodologies and workflows.
• Support post-silicon validation and yield optimization.
• Maintain design documentation and validation results.

Skills

Analog IC design

CMOS technology

SPICE simulations

Lab testing

SoC integration

Cryogenic exposure

Education

Master's or PhD in Electrical Engineering

Microelectronics focus

Tools

Cadence Virtuoso

SPICE

Job description

Darwin Recruitment is seeking a Staff / Senior Staff Analog IC Design Engineer to drive the development of high‑performance analog/mixed‑signal ICs for advanced semiconductor applications. The role involves circuit design, verification, and collaboration with cross‑functional teams to deliver robust IP for SoCs.

Responsibilities include schematic design, SPICE simulations, layout coordination, and post‑silicon validation, with opportunities to explore cryogenic environments where applicable.