RTL Design Engineer - PPA Optimization & Verilog Expert

BITMAIN; Singapore; On-site; SGD 90,000 - 140,000; Full time

Job summary

BITMAIN is seeking a chip design engineer in Singapore to define product specifications, analyze algorithms, and develop module-level specs. The role involves RTL implementation and verification with a focus on PPA optimization.

Responsibilities include digital circuit synthesis, timing analysis, and related design tasks. Proficiency in Verilog/SystemVerilog and scripting languages is required; experience with SDC constraints and Netlist ECO flows is expected.

Qualifications

• Experience in algorithm-based digital circuits.
• PPA optimization or ultra-low-power design preferred.
• Proficient in Verilog/SystemVerilog and scripting languages (Python/Tcl/Shell/Perl).
• Familiar with SDC constraints and Netlist ECO flows; knowledge of UVM is a plus.

Responsibilities

• Participate in chip product specification definition, including algorithm analysis and module-level specification development.
• Implement and verify digital circuits at the RTL level, performing PPA optimization.
• Conduct digital circuit synthesis, timing analysis, and related design tasks.

Skills

Verilog/SystemVerilog

RTL design

Scripting languages (Python/Tcl/Shell/

Tools

VCS

Verdi

DC

Formality

SpyGlass

Job description

BITMAIN is seeking a chip design engineer in Singapore to define product specifications, analyze algorithms, and develop module-level specs. The role involves RTL implementation and verification with a focus on PPA optimization.

Responsibilities include digital circuit synthesis, timing analysis, and related design tasks. Proficiency in Verilog/SystemVerilog and scripting languages is required; experience with SDC constraints and Netlist ECO flows is expected.