Layout Engineer

Broadcom; Singapore; On-site; SGD 70,000 - 110,000; Full time

Job summary

Broadcom is seeking a Layout Engineer in Singapore to contribute to memory, I/O, and standard cell layouts within the Library Group of the Central Engineering Group.

The role requires 2–3 years of IC layout experience, strong Cadence layout and verification tool skills (Calibre, Hercules), and familiarity with submicron nodes from 16nm down to 1.4nm. Analog layout experience is a plus.

Qualifications

• 2–3 years of IC layout experience.
• Strong memory, I/O, and standard cell layout experience.
• Experience with submicron nodes (16nm to 1.4nm and below).
• LVS/DRC/ERC and reliability checks experience.
• Familiarity with advanced process rules and layout guidelines.

Responsibilities

• Understand and apply layout guidelines for standard cells, I/O, and memories.
• Plan schedules and perform floor-planning for layouts.
• Deliver quality layout and verification within schedule with minimal supervision for experienced engineers.
• Adapt quickly to new methodologies and communicate effectively with the library team.

Skills

Cadence layout

Cadence schematic capture

CALIBRE

Hercules verification

Memory layout design

Digital (standard cell, memory, I/O)

Analog layout

Floor-planning

Chip integration

VIRTUOSO

SKILL programming

Scripting

Memory topology

Memory compiler

Teamwork

Tools

Cadence Virtuoso XL/VXL/EXL

CALIBRE

Job description

Job Description:

Layout Engineer

Job descriptions and the level of expertise:

The descriptions are for layout engineers for our Library Group. Library Group is a part of Central Engineering Group.

In Library Group, we focus on circuit design for memory, I/O (Input/Output), and Standard Cells.

Requirements:

IC Layout

Strong layout knowledge with a minimum of 2 to 3 years of experience

Skills include Cadence layout, Cadence schematic capture, using CALIBRE & Hercules verification tools.

Strong layout knowledge in submicron process, e.g. 16nm, 7nm, 5nm,2nm, 1.4nm and below

Experienced in digital (standard cell, memory, I/O) layout

Experienced in analog layout is also a plus

Job description:

IC Layout

Responsible to understand and apply all necessary layout guidelines (standard cells, I/O memories), new process rules and other technical requirements for quality layout

Schedule time-line & layout floor-planning

Complete quality layout and verification within planned schedule (without supervision for experienced engineer)

Get up to speed quickly for new methodologies, open to new ideas and communicate well with others in the library team

Skill Set (Mem)

• Strong experience in memory layout design and physical verifications includes LVS, DRC, ERC, Antenna, Electro Migration in CMOS process.
• Experienced in Cadence Layout tools VIRTUOSO (XL,VXL or EXL), and CALIBRE verification tools.
• Good experience in Floor-planning, hierarchy layout and chip integration.
• Knowledge of Script Programming and SKILL Programming would be a plus.
• Good knowledge on memory layout topology.
• Experience in memory compiler will be a plus.
• Ability to adapt on new technology reviews to compile documentation of layout methodology, layout flow and guidelines.
• Self-reliant, with ability to work independently as well as a team.