Lead SoC Design Verification Engineer

Bitdeer (NASDAQ: BTDR); Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Bitdeer is seeking a highly motivated Design Verification Lead to drive verification strategy for complex IC designs. You will lead a team of verification engineers to ensure robust coverage and high-quality silicon through advanced verification methodologies and close collaboration with design and architecture teams.

The role requires at least 10 years of IC/SoC functional verification experience, strong RTL debugging, and proficiency in UVM, SystemVerilog, Verilog, SVA, plus AXI, NoC and

Qualifications

• 10+ years of IC/SoC functional verification experience
• Strong debugging skills with RTL simulation and waveform analysis
• Proficient in UVM, SystemVerilog, Verilog, and SVA languages
• Knowledge of AXI, NoC and RISC-V protocols
• Proven ability to lead verification efforts and mentor engineers
• Excellent communication and collaboration in cross-functional teams

Responsibilities

• Lead the verification strategy and execution for DUT blocks with full coverage
• Develop and maintain verification test plans aligned with design specs
• Create verification environments, testbenches, and sequences
• Generate test patterns and stimuli to validate functionality and corner cases
• Run simulations, analyze results, and debug RTL issues with design engineers
• Manage regression testing to ensure stability across updates
• Track coverage metrics and sign-off readiness
• Develop automation scripts and Verification IP to boost productivity
• Collaborate with design, architecture, and physical implementation teams
• Mentor junior team members

Skills

RTL debugging

UVM

SystemVerilog

Verilog

SVA

AXI

NoC

RISC-V

Mentoring

Communication

Education

Bachelor's degree or above in Microelectronics/Semiconductor/Electrical Engineering

Job description

Bitdeer is seeking a highly motivated Design Verification Lead to drive verification strategy for complex IC designs. You will lead a team of verification engineers to ensure robust coverage and high-quality silicon through advanced verification methodologies and close collaboration with design and architecture teams.

The role requires at least 10 years of IC/SoC functional verification experience, strong RTL debugging, and proficiency in UVM, SystemVerilog, Verilog, SVA, plus AXI, NoC and