Lead Process Integration Engineer (CMOS)

SSMC; Singapore; Hybrid; SGD 180,000 - 240,000; Full time

Job summary

SSMC in Singapore seeks a Principal Engineer, Process Integration – TSMC to drive CMOS fabrication tech development, transfer, and high-yield production. You will own tapeouts, lead cross-functional improvements, and mentor engineers while coordinating with TSMC mother fabs.

Ideal candidates bring 5+ years in semiconductor FABs, strong CMOS/Flash/NVM knowledge, and leadership skills to push 100% wafer acceptance and Cpk targets. Mandarin communication is a plus for TSMC collaboration.

Qualifications

• Master's or Bachelor's degree in Electrical/Electronic Engineering or equivalent.
• Minimum 5 years of relevant experience in semiconductor FAB environment.
• Strong CMOS/Flash/NVM/HV wafer fabrication knowledge.
• Proficient in SPC, 8D problem solving and decision making.
• Automotive Quality Mindset and Stop & Fix mindset.

Responsibilities

• Lead development, transfer and maintenance of advanced CMOS fabrication tech with high yield.
• Manage integration of modules’ processes and derivatives.
• Lead technology transfer from mother fab or process development.
• Own tapeout prototype lots and ensure 100% success rate.
• Drive process robustness and root-cause analysis to meet wafer acceptance & Cpk goals.
• Collaborate with CAM to resolve customer concerns and provide info.
• Mentor and train engineers; interact with TSMC mother fabs for alignment.
• Lead cross-functional continuous improvement projects.

Skills

CMOS fabrication

Flash memory fabrication

SPC

8D problem solving

Leadership

Presentation & communication

Mentorship

Education

Electronics engineering degree

Tools

PROMIS system

Klarity ACE

JMP

Minitab

Job description

SSMC in Singapore seeks a Principal Engineer, Process Integration – TSMC to drive CMOS fabrication tech development, transfer, and high-yield production. You will own tapeouts, lead cross-functional improvements, and mentor engineers while coordinating with TSMC mother fabs.

Ideal candidates bring 5+ years in semiconductor FABs, strong CMOS/Flash/NVM knowledge, and leadership skills to push 100% wafer acceptance and Cpk targets. Mandarin communication is a plus for TSMC collaboration.