Gen‑AI Research Engineer: In-Memory Compute & Chips

National University of Singapore; Singapore; On-site; SGD 60,000 - 100,000; Full time

Job summary

The National University of Singapore is seeking a Research Engineer (Gen-AI) for the OUTSMART Corp Lab within the Department of Electrical and Computer Engineering. The appointment is a 1-year contract with possibility of extension and will commence immediately on Kent Ridge Campus.

Responsibilities include circuit exploration for near-PCM and in-memory SRAM computing macros, experimental validation of macros and dataflow adaptation, and testing across single and multi-chiplet configurations.

Qualifications

• Bachelor’s degree in Electrical Engineering or related field
• Knowledge of circuit architectures and transistor-level design
• Experience with silicon chip design and EDA tools
• Ability to work independently and in a team
• Good communication and interpersonal skills
• Open to fixed-term contract

Responsibilities

• Explore near-PCM and in-memory SRAM computing macros
• Experimentally validate computing and memory macros and dataflow adaptation
• Validate test structures with dataflow adaptation in single chip and high memory-logic interspersion
• Validate chiplet interfaces and synchronization across chiplets
• Experimentally validate final testchip in single- and multi-chiplet arrangements
• Validate final testchip in single-chiplet arrangement

Skills

Circuit architectures

Transistor-level design

Silicon chip design

EDA tools

Independent work

Communication skills

Education

Bachelor's in Electrical Engineering

Tools

EDA tools

Job description

The National University of Singapore is seeking a Research Engineer (Gen-AI) for the OUTSMART Corp Lab within the Department of Electrical and Computer Engineering. The appointment is a 1-year contract with possibility of extension and will commence immediately on Kent Ridge Campus.

Responsibilities include circuit exploration for near-PCM and in-memory SRAM computing macros, experimental validation of macros and dataflow adaptation, and testing across single and multi-chiplet configurations.