FPGA Hardware Acceleration Engineer

China Telecom Singapore Innovation Research Institute; Singapore; Sur place; SGD 90 000 - 150 000; Plein temps

Résumé du poste

China Telecom Singapore Innovation and Research Institute is seeking an FPGA Hardware Acceleration Engineer to design and deploy high-performance compute pipelines on modern heterogeneous silicon (AMD Versal AI Edge).

You will own the hardware acceleration data paths from RTL/HLS implementation to physical board bring-up, collaborating with AI research scientists and embedded software engineers to ensure deterministic execution and low latency.

Qualifications

• Master's degree or above in Electrical/Electronic Engineering or Computer Engineering.
• Proven FPGA design flow from RTL/HLS to validation on hardware.
• Experience with DMA engines, PCIe, or memory controllers.

Responsabilités

• Design and deploy high-performance compute pipelines on heterogeneous silicon.
• Develop custom compute engines and streaming data paths.
• Collaborate with AI and software teams to integrate FPGA kernels.

Connaissances

FPGA design experience

Low latency optimization

Hardware-software collaboration

Formation

Master's degree or higher in E/ECE or CS

Outils

Verilog/VHDL

Vitis HLS (C/C++)

Vivado toolchain

AXI4/AXI-Stream

PCIe DMA

Description du poste

China Telecom Singapore Innovation and Research Institute (CTSIRI) is seeking an FPGA Hardware Acceleration Engineer to design and deploy high-performance compute pipelines on modern heterogeneous silicon (AMD Versal AI Edge).

You will own the hardware acceleration data paths from RTL/HLS implementation to physical board bring-up. Our AI and software teams provide the algorithms and high-level software stacks—your focus is silicon performance, low latency, and deterministic execution.

Key Responsibilities

• Develop custom compute engines and streaming data paths using Verilog or C/C++ High-Level Synthesis (HLS).
• Build high-throughput memory and streaming interfaces using AXI4, AXI-Stream, and DMA to minimize latency.
• Lead logic synthesis, place-and-route, and timing closure within the AMD Vivado / Vitis / Vitis AI toolchain.
• Validate and debug designs on physical evaluation boards using logic analysers, and hardware-in-the-loop testbeds.
• Collaborate with AI research scientists and embedded software engineers to integrate FPGA kernels with ARM host processors.

Qualifications

• Master's degree or above in Electrical/Electronic Engineering, Computer Engineering, or a related field.
• Practical track record of taking FPGA designs through RTL/HLS, simulation, synthesis, and on-board hardware validation.
• Exposure to DMA engines, PCIe, or DDR4/LPDDR memory controllers.
• Proficiency in SystemVerilog/VHDL or Vitis HLS (C/C++).
• Familiarity with latest Vivado / Vitis and timing analysis.
• Good grasp of pipelining, memory hierarchy, and on-chip bus protocols (AXI4 / AXI-Stream).