E5_MTS_SMTS NAND Design Rule Engineer in Process Integration

Micron; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Micron Technology Singapore is seeking an experienced NAND Design Rule / Process Integration engineer to support development and high‑volume manufacturing of advanced 3D NAND technologies.

You will lead design-rule deliverables, coordinate with cross‑functional teams, ensure quality and documentation for DRCs, and drive continuous improvements across R&D and production programs. This role requires strong CAD skills and deep knowledge of 3D NAND processes.

Qualifications

• PhD in Electrical Engineering or related field with 5+ years in semiconductors.
• Hands-on with PDK, design rule, and layout; CAD tools mandatory.
• Strong 3D NAND process flow knowledge.

Responsibilities

• Lead the release of design rules and PDK deliverables; manage DRC waivers, mask reviews for both R&D and production designs.
• Own program execution and milestones from kickoff through end-of-life.
• Collaborate with Yield Enhancement, Product Engineering, Defect Analysis, and Quality Assurance to identify issues and prioritize corrective actions.
• Design and evaluate test structures to generate data for next-generation devices and to assess process margin on current technologies.
• Synthesize complex technical problems and communicate status, risks, and resolutions clearly across functions.

Skills

PDK experience

Design rules

Layout experience

VLSI physics

Data analysis

Education

PhD in Electrical Engineering

MS in Microelectronics

Bachelor's in Semiconductor

Tools

Cadence Virtuoso

K2View

Mentor DRC/RVE

Job description

Our vision is to transform how the world uses information to enrich life for all.

Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing.

As a E5/MTS/SMTS NAND Design Rule / Process Integration engineer, your role is to support the development and high-volume manufacturing of advanced 3D NAND technologies. This role drives design-rule and PDK deliverables, partners closely across process integration and design organizations, and ensures quality, documentation, and timely execution across R&D and production programs.

• Lead the release of design rules and PDK deliverables; manage DRC waivers, mask definitions, and mask reviews for both R&D and production designs.
• Own program execution and milestones from kickoff through end-of-life.
• Partner with stakeholders across Array & CMOS Process Integration, Devices, Layout & Design, Modeling, Scribe & Frame, unit process areas (e.g., PHOTO/OPC/CMP), and Quality & Reliability to guide new 3D NAND generations.
• Ensure high quality and documentation for Design Rule Checks (DRCs) and drive timely disposition of deviations and exceptions.
• Collaborate with Yield Enhancement, Product Engineering, Defect Analysis, and Quality Assurance to identify layout- or database-related process issues and prioritize corrective actions.
• Design and evaluate test structures to generate data for next-generation devices and to assess process margin on current technologies.
• Synthesize complex technical problems and communicate status, risks, and resolutions clearly across functions and management levels.
• Define and track sub-milestones within PDK/DBR/TO schedules; ensure targets are met through cross-team coordination.
• Maintain strong, proactive communication with key stakeholders and elevate issues early with data-driven options.
• Drive continuous improvement in design-rule pathfinding and document learnings that improve production parts still in design.

Requirements

• Education/experience: PhD in Electrical Engineering, Microelectronics, Physics, or Semiconductor Materials Science with 5+ years of relevant experience; or Master's degree with 8+ years; or bachelor's degree with 13+ years in the semiconductor industry (Process Integration, Yield Enhancement, Product Engineering, Test Structure Development, or Unit Process Development).
• Hands-on exposure to PDK, design rule, and layout (including minor layout work); proficiency with CAD tools such as Cadence Virtuoso, K2View, and Mentor Graphics DRC/RVE (or equivalent) is a MUST.
• Strong semiconductor device physics and VLSI silicon processing and integration flow knowledge is a MUST.
• Demonstrated ability to resolve complex issues and communicate clearly under pressure.
• Understanding of 3D NAND process flow and major NAND components (e.g., bit-line sensing, word-line driver, data path, and analog circuits).
• Familiarity with CAD group interactions, data post-processing, and data transfer from design databases to reticles.
• Preferred: prior experience in R&D for NAND or other memory technologies.

About Micron Technology, Inc.

We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities - from the data center to the intelligent edge and across the client and mobile user experience.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

To request assistance with the application process and/or for reasonable accommodations, please contact [e-mail]

Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.

Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.

AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misr