NAND Design Rule Manager

Micron; Singapore; On-site; SGD 180,000 - 280,000; Full time

Job summary

Micron Technology, Inc. seeks a Manager for NAND Design Rule/Process Integration in Singapore to lead a team responsible for design-rule and PDK development for 3D NAND production.

You will drive program execution, coordinate cross-functional activities with CMOS, device, and layout teams, ensure high-quality documentation, and mentor team members while advancing next-generation memory technologies.

Qualifications

• PhD in Electrical Engineering, Microelectronics, Physics, or Semiconductor Materials Science with 5+ years in the semiconductor industry.
• Experience with PDK, design rules, and layout, including small layout tasks.
• Solid understanding of semiconductor device physics and VLSI silicon processing and integration flow.
• Ability to resolve complex issues and communicate clearly under pressure.
• Understanding of 3D NAND process flow and major NAND components.

Responsibilities

• Lead release of design rules and PDK deliverables; coordinate DRC waivers, mask definitions, and mask reviews for both R&D and production developments.
• Own program execution and achievements from kickoff through end-of-life.
• Partner with collaborators across Array & CMOS Process Integration, Devices, Layout & Build, Modeling, Scribe & Frame, unit process areas (e.g., PHOTO/OPC/CMP), and Quality & Reliability to guide new 3D NAND generations.
• Ensure high quality and documentation for Build Rule Checks (DRCs) and drive timely disposition of deviations and exceptions.
• Collaborate with Yield Improvement, Product Engineering, Defect Analysis, and Quality Assurance to identify layout- or database-related process issues and prioritize corrective actions.
• Build and evaluate test structures to generate data for next-generation devices and to assess process margin on current technologies.
• Synthesize complex technical problems and communicate status, risks, and resolutions clearly across functions and management levels.
• Define and track sub-milestones within PDK/DBR/TO schedules; ensure targets are met through cross-team coordination.
• Maintain strong, proactive communication with key collaborators and bring up issues early with data-driven options.
• Drive continuous improvement in design-rule pathfinding and document takeaways that improve production parts still under development.

Skills

PDK work

Design rules

Layout CAD

Leadership

Education

PhD in Electrical Engineering or related field

Master's with 8+ years

Bachelor's with 13+ years

Tools

Cadence Virtuoso

K2View

Mentor Graphics DRC/RVE

Job description

Our vision is to transform how the world uses information to enrich life for all.

Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing.

Join Micron, where your knowledge will influence the future of memory technology! As the Manager for NAND Design Rule/Process Integration, you will lead a talented team to support both development and large-scale production of advanced 3D NAND technologies. This position is essential for producing accurate design-rule and PDK results, ensuring high quality, and maintaining strict documentation across R&D and production efforts.

Responsibilities:

• Lead the release of design rules and PDK deliverables; coordinate DRC waivers, mask definitions, and mask reviews for both R&D and production developments.
• Own program execution and achievements from kickoff through end-of-life.
• Partner with collaborators across Array & CMOS Process Integration, Devices, Layout & Build, Modeling, Scribe & Frame, unit process areas (e.g., PHOTO/OPC/CMP), and Quality & Reliability to guide new 3D NAND generations.
• Ensure high quality and documentation for Build Rule Checks (DRCs) and drive timely disposition of deviations and exceptions.
• Collaborate with Yield Improvement, Product Engineering, Defect Analysis, and Quality Assurance to identify layout- or database-related process issues and prioritize corrective actions.
• Build and evaluate test structures to generate data for next-generation devices and to assess process margin on current technologies.
• Synthesize complex technical problems and communicate status, risks, and resolutions clearly across functions and management levels.
• Define and track sub-milestones within PDK/DBR/TO schedules; ensure targets are met through cross-team coordination.
• Maintain strong, proactive communication with key collaborators and bring up issues early with data-driven options.
• Drive continuous improvement in design-rule pathfinding and document takeaways that improve production parts still under development.

Requirements:

• PhD in Electrical Engineering, Microelectronics, Physics, or Semiconductor Materials Science with 5+ years of relevant experience; or Master's degree with 8+ years; or bachelor's degree with 13+ years in the semiconductor industry (Process Integration, Yield Improvement, Product Engineering, Test Structure Development, or Unit Process Development).
• Direct experience working with PDK, design rules, and layout, including small layout assignments, is necessary. You must be skilled in CAD software such as Cadence Virtuoso, K2View, and Mentor Graphics DRC/RVE or their equivalents.
• A solid understanding of semiconductor device physics and VLSI silicon processing and integration flow is essential.
• Demonstrated ability to resolve complex issues and communicate clearly under pressure.
• Understanding of 3D NAND process flow and major NAND components (e.g., bit-line sensing, word-line driver, data path, and analog circuits).
• Familiarity with CAD group interactions, data post-processing, and data transfer from built databases to reticles.
• Preferred: prior leadership experience in R&D for NAND or other memory technologies.

Micron Technology is transforming how information is used globally by advancing memory and storage solutions. The company emphasizes innovation, collaboration, integrity, and professionalism, and is committed to supporting its global community while conducting business responsibly. Join us and be part of a world-class team that competes at the highest levels and successfully implements groundbreaking solutions!

About Micron Technology, Inc.

We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities - from the data center to the intelligent edge and across the client and mobile user experience.

To learn more, please visit micron.com/careers

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

To request assistance with the application process and/or for reasonable accommodations, please contact [e-mail]

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