Design Verification Engineer II - Hybrid, Low-Power IoT

Silicon Labs; Singapore; On-site; SGD 110,000 - 170,000; Full time

Benefits offered by this job

Medical and dental insurance coverage

Bi yearly health screening

Office above Tai Seng MRT station

Job summary

Silicon Labs, a leader in low-power wireless connectivity, seeks a senior verification engineer for its IoT Digital Design team in Singapore. You will develop and execute verification plans for SoC/IP blocks, build SystemVerilog/UVM testbenches, and drive coverage, assertions, and regression across mixed-signal designs.

You will collaborate with RTL, architecture, firmware, and validation teams, mentor junior engineers, and help shape verification strategy for pre- and post-silicon activities.

Qualifications

• BS/MS in Electrical or Computer Engineering or equivalent.
• 5–10+ years of verification experience in semiconductor projects.
• Experience with Wireless SoCs and low-power IoT silicon.

Responsibilities

• Develop and execute verification plans for SoC/IP blocks and mixed-signal designs.
• Build and maintain SystemVerilog/UVM-based testbenches; create constrained-random tests.
• Drive functional coverage closure, assertions, and regression analysis; debug RTL/verification issues.

Skills

SystemVerilog

UVM/OVM

RTL/GLS simulation/debug

Functional coverage

Assertions (SVA)

SoC/IP verification

Low-power verification concepts

CDC/RDC verification

Mixed signal / AMS verification

Education

BS/MS in Electrical or Computer Engineering

Tools

Python scripting

Perl scripting

TCL scripting

Job description

Silicon Labs, a leader in low-power wireless connectivity, seeks a senior verification engineer for its IoT Digital Design team in Singapore. You will develop and execute verification plans for SoC/IP blocks, build SystemVerilog/UVM testbenches, and drive coverage, assertions, and regression across mixed-signal designs.

You will collaborate with RTL, architecture, firmware, and validation teams, mentor junior engineers, and help shape verification strategy for pre- and post-silicon activities.