CNFET Process Fellow: Wafer-Scale CMOS Innovation

National University of Singapore; Singapore; On-site; SGD 70,000 - 110,000; Full time

Job summary

National University of Singapore’s Department of Electrical and Computer Engineering is seeking a Research Fellow to lead the CNFET process development and device integration for wafer-scale carbon nanotube CMOS. You will develop ALD high-k gate stacks, metal contacts, channel cleaning, and BEOL-compatible integration, with transfer to an industry partner for 200 mm validation.

You will build a robust process-of-record, supervise graduate students, publish results, and contribute to proposals,

Qualifications

• PhD in Electrical Engineering, Materials Science, Applied Physics, Chemical Engineering or closely related field (awarded or thesis submitted at time of application).
• Hands-on cleanroom experience covering ALD, lithography, etching, PVD/evaporation, and wet processing.
• Ability to take a device from mask design through fabrication to working electrical data.
• Electrical characterisation of nanoscale transistors with statistical analysis to separate effects.
• Strong publication record, fluent English, and ability to work independently and guide junior researchers.

Responsibilities

• Lead process development and device fabrication for CNFET on wafer-scale.
• Qualify carbon nanotube array film as a device-grade channel material using SEM, AFM, Raman, and optical mapping.
• Characterise devices electrically and statistically – transfer and output characteristics, contact resistance, subthreshold swing, hysteresis, distributions.
• Author the process-of-record (flow sheet, recipes, metrology plan) and support lab-to-fab transfer to partner line.
• Publish results, supervise graduate students in the cleanroom, contribute to proposals.

Skills

Cleanroom experience

Device fabrication

Electrical characterization

English communication

Research supervision

Education

PhD in Electrical Engineering or related field

Tools

ALD

Electron-beam lithography

Stepper lithography

RIE

PVD

Wet processing

Job description

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Research Fellow (Carbon Nanotube CMOS Process Development and Device Integration)

University-Level Unit: College of Design and Engineering Faculty/Department-Level Unit: Electrical and Computer Engineering Employee Category: Research Staff Location_ONB: Kent Ridge Campus Posting Start Date: 26/08/2026

Job Description

The Department of Electrical and Computer Engineering (ECE), College of Design and Engineering, is seeking a Research Fellow to lead the process development and device fabrication track of a research programme on wafer-scale carbon nanotube CMOS. The work runs on two tracks: process modules are developed and optimised on coupon-scale samples at NUS, then transferred as a documented process-of-record to an industry partner for verification on a 200 mm line.
Key responsibilities:
• Develop and optimise the core CNFET process modules — ALD high-k gate stacks, source/drain contact metallisation, channel cleaning and passivation, and threshold-voltage control — within a BEOL-compatible (≤ 400 °C) thermal budget.
• Build a silicon-fab-compatible contact integration scheme using only unit processes a production line already runs, and scale the device geometry to aggressive contacted gate pitch by electron-beam or DUV lithography.
• Qualify incoming carbon nanotube array film as a device-grade channel material (density, alignment, uniformity, purity, residues) by SEM, AFM, Raman and optical mapping, and define acceptance criteria.
• Characterise devices electrically and statistically — transfer and output characteristics, contact resistance, subthreshold swing, hysteresis, threshold distributions and basic reliability screening.
• Author the process-of-record (flow sheet, recipes, metrology plan, in-line control limits) and support its lab-to-fab transfer to the partner line, including joint failure analysis and corrective process splits.
• Develop an CNFET module for complementary operation, and fabricate CNFET integrated circuits in collaboration with the circuit design team.
• Publish in leading venues, supervise graduate students in the cleanroom, and contribute to invention disclosures and research proposals.

Qualifications

Essential:
• PhD in Electrical Engineering, Materials Science, Applied Physics, Chemical Engineering or a closely related field (awarded, or thesis submitted, at the time of application).
• Substantial hands-on cleanroom experience covering a credible fraction of: atomic layer deposition, electron-beam and/or stepper lithography, reactive ion etching, physical vapour deposition and evaporation, and wet processing.
• Demonstrated ability to take a device from mask design through fabrication to working electrical data — the whole flow, not a single module.
• Electrical characterisation of nanoscale transistors (semiconductor parameter analyser, probe station), with the statistical discipline to separate a real process effect from a lucky device.
• A publication record commensurate with career stage, strong written and spoken English, and the ability to work independently and to guide junior researchers.
Desirable:
• Device fabrication on nanomaterials — carbon nanotubes, 2D materials or nanowires.
• Contact engineering and contact-resistance reduction on low-dimensional channels; work-function engineering for complementary operation.
• Low-temperature / BEOL-compatible integration or monolithic 3D process experience.
• Exposure to a 200 mm or 300 mm production environment, or prior collaboration with a foundry, including what it takes to make a recipe transferable.
• Design of experiments, statistical process control, and in-line metrology.
• Cleanroom tool ownership and safety leadership.

Req ID: 34219 Apply now

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