Senior FPGA Engineer

Swediumglobal; Stockholms kommun; On-site; SEK 533,960 - 747,544; Full time

Job summary

A growing System Engineering and Solution Company is seeking an experienced FPGA Design Engineer in Sweden. The role requires 4+ years of HDL design expertise, proficient knowledge in System Verilog, and familiarity with FPGA vendor IP integration. Responsibilities include optimizing timing-critical designs and verifying implementations using System Verilog and Python. This position offers an onsite opportunity to work on cutting-edge semiconductor engineering projects.

Qualifications

• 4+ years of experience in HDL design for FPGA implementation.
• Proficient in System Verilog and design of custom modules.
• Experience with integration and configuration of FPGA Vendor IPs.

Responsibilities

• Design and implement timing-critical FPGA projects.
• Optimize algorithms at the RTL level.
• Verify designs using System Verilog and Python.

Skills

HDL design experience

System Verilog

FPGA design

Python scripting

Timing analysis

Digital Signal Processing fundamentals

Tools

Vivado

Electronics lab tools

Job description

Swedium Global is the growing System Engineering and Solution Company, offers services like Semiconductor Engineering R&D Services, Embedded Systems Development, Custom Application Software Development, Web and Cloud Application Development, Testing Services, Consultancy and Outsourcing services to our clients across the globe for an onsite and offshore business model. Swedium Global is having presence in Sweden, Finland, Poland, Czech Republic and in India.

Location- Onsite,Sweden

Role Overivew

• 4+ years of experience in HDL design in a multi-clock environment for FPGA implementation
• System Verilog as main HDL
• Worked with medium to large designs
• Experience of designing and working with fully custom, in-house built System Verilog modules
• Experience of working with integration and configuration of FPGA Vendor IPs
• Optimization of calculation heavy algorithms on RTL level
• STA analysis and requirements
• Experienced in timing-critical FPGA design and timing closure
• Experience in writing timing constraints for multi-clock domain designs
• Verification using System Verilog and Python
• Worked with SOC FPGAs, i.e. with hardened CPU
• High speed IO, DDR , PCIe and MIPI
• Use of Vivado ILA
• Scripting, mainly in Python
• Electronics and Electronic lab tools fundamentals (Multimeter, Osciloscope)
• Digital Signal Processing fundamentals
• Comfortable with simulation tools and writing testbenches