Baseband SoC Architect: DSP/CPU, Parallel Systems

Huawei Sweden; Kista; On-site; SEK 900,000 - 1,200,000; Full time

Job description

Responsibilities

• Design the SoC architecture for the 5.5/6G wireless baseband chip, focusing on the next‑generation computing architecture to meet increasing demand for computing power.
• Design, evaluate, and integrate cutting‑edge IP to ensure architectural leadership; address challenging architectural bottlenecks through simulation and research.
• Collaborate with algorithm experts, hardware engineers, and software specialists; maintain close coordination with the core team in Shanghai and participate in tackling critical wireless technology challenges.

Qualifications and Experience

The ideal candidate will have over five years of industrial or academic experience in SoC areas such as processors, interconnects, interfaces, scheduling, cache/DMA, memory systems, power consumption, and design methodology. They should possess knowledge of software and hardware architecture design for large‑scale parallel computing, and have hands‑on skills in block design with Verilog or VHDL.

• Knowledge in wireless physical layer applications is preferred.
• Experience in designing DSP, ARM, or CPU micro‑architecture.
• Experience in designing vector, matrix, or graph processors.
• Experience in designing SRAM, DRAM, or cache systems.
• Experience in designing AI‑based computing architecture.
• Experience in designing SoC systems.
• Experience in developing multi‑threaded software.
• A Ph.D. in electrical engineering, computer architecture, or an equivalent background is required.

Other

• Highly developed skills in finding innovative solutions, strategic vision, and the ability to lead and drive activities.
• Prior experience with international and multicultural work environments is preferred.
• Fluency in English, both verbal and written.