ASIC/FPGA Design Engineer

Chipright; Sweden; Sur place; SEK 613 800 - 781 200; Plein temps

Résumé du poste

A leading technology firm is seeking a Digital IP Developer for a full-time role in Lund, Sweden. The ideal candidate will have extensive experience in ASIC/FPGA design, specifically with RTL design in System Verilog and UVM verification methodologies. Responsibilities include driving verification projects and collaborating with cross-functional teams. English and Swedish language skills are required.

Qualifications

• At least 7 years in the ASIC/FPGA industry.
• Proficient in verification planning, reporting.
• Experience with IP and system level verification.

Responsabilités

• Drive verification processes from start to finish.
• Collaborate with System Architects and Integration teams.
• Report and drive verification closure.

Connaissances

RTL design in System Verilog

Verification using UVM methodology

Communication skills

UNIX/Linux experience

Strong collaborative skills

Agile methodologies

Scripting in Perl, Python, Bash

Outils

Jasper

OneSpin

InFact

Clearcase

Description du poste

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Digital IP Developer profile

For our client we are looking for a Digital IP Developer profile Mandatory:• Proficient with both RTL design in System Verilog and verification using UVM methodology• Strong collaborative skills with System Architects and Integration teams• Proficient in verification planning, reporting and driving verification closure. Must understand how a verificationproject works, from start to finish• Experience with IP level and system level verification• Strong team player• Excellent communication skills, both written and oral English• Experience with UNIX and/or Linux• At least 7 years in ASIC/FPGA industry• Strong work ethics Meritorious:• Experience with UART, SPI, I3C protocols• Experience with analog-mixed-signal type ASICs• Experience using formal properties and tools, such as Jasper, OneSpin, InFact and similar• Experience in using golden models/reference models in a test bench• Experience in agile ways of working, agile scrum• Clearcase version control system experience• VHDL knowledge• C-programming• Scripting in Perl, Python, Bash or C-shell• More than 10 years in the ASIC/FPGA industry• Ability to travel to Kista, Stockholm once per every second month Start: ASAPDuration: 6-12 monthsLocation: LundWork load: Full-time OnsiteWorking language: English and Swedish