Senior Digital Design Engineer — FPGA/ASIC RTL Lead

Skydrop; Riyadh; On-site; SAR 262,467 - 374,953; Full time

Job summary

Skydrop is seeking an experienced Digital Design Engineer to lead RTL design and verification for digital subsystems. In this role, you'll impact the development and execution of high-performance designs in FPGA and ASIC environments. Candidates should have 5-10 years of experience, strong proficiency in SystemVerilog and/or VHDL, and an expert understanding of synchronous design principles. A command of timing closure and debugging skills is essential, and experience mentoring junior engineers is desired.

Qualifications

• 5–10 years of industry experience in digital IC or FPGA design.
• Strong proficiency in SystemVerilog and/or VHDL.
• Expert-level understanding of synchronous design principles.
• Working knowledge of STA and timing exceptions.
• Proficient in Python and/or Tcl for automation.

Responsibilities

• Lead RTL design and verification efforts for FPGA and ASIC targets.
• Architect and implement synthesizable RTL in VHDL or SystemVerilog.
• Define and execute verification strategies using SystemVerilog.
• Drive STA and timing constraint development.
• Lead hardware validation and debug.

Skills

HDL expertise

Digital design depth

Verification competence

Scripting & automation

Communication

Tools

SystemVerilog

VHDL

Xilinx Vivado

Cadence Genus

Git

Job description

Skydrop is seeking an experienced Digital Design Engineer to lead RTL design and verification for digital subsystems. In this role, you'll impact the development and execution of high-performance designs in FPGA and ASIC environments. Candidates should have 5-10 years of experience, strong proficiency in SystemVerilog and/or VHDL, and an expert understanding of synchronous design principles. A command of timing closure and debugging skills is essential, and experience mentoring junior engineers is desired.