Principal Verification Engineer

Job Title : Principal Digital Verification Engineer

Job Type : Permanent

Start : ASAP

Our client-

We are working with a “solution SoC” company with rich experience in different markets leading innovations with customers around the world.

In the fields of “automotive”, “data centre & networking”, and “smart devices”, functionality and performance are becoming increasingly sophisticated, they design and develop their products based on common concepts, including subsystem configuration and bus architecture, and deliver SoCs that meet their scalability needs and enable the optimal function and performance for each application.

Responsibilities-

• You work with engineers of the Design Team and Verification Team to carry out the Design Verification (SpecmanE, UVM)
• You proceed with development (design and verification) in compliance with ISO (Functional Safety)
• You work with safety manager, project manager and development team on functional safety work products.

Profile -

• You have a degree in electrical engineering, computer science or similar.
• You have solid experience (8+ years) in the area of design verification.
• You have led the verification team performing verification tasks according to the functional safety processes.
• You are not only proficient in hardware description languages (Verilog, VHDL, SystemC, SystemVerilog), but bring extensive experience across the entire SoC design flow.
• You have experience in functional safety and in the use of relevant tools and methods.
• You have experience with CADENCE tools for Functional Verification like Xcelium, VManager, Specman / e and JasperGold.