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Job Description: Hardware Verification Engineer at Eclipse Foundation Europe GmbH

The Eclipse Foundation Europe GmbH is hiring a Hardware Verification Engineer for its OpenHW Foundation. Working as a member of the Eclipse Research Team, the candidate will verify industrial-grade open-source IPs based on RISC-V, including but not limited to:

• Lock-step execution of dual-core systems based on CVA6
• Cache-coherency blocks
• Hypervisor ISA Extensions
• IO Memory-Management Units
• Advanced Interrupt Architecture

This role involves contributing to the verification of the CVE2 core for the TRISTAN project, then switching to the Rigoletto project, both EU-funded projects, for approximately 3 years.

The TRISTAN project aims to expand and industrialize the European RISC-V ecosystem, providing European digital sovereignty through open-source IPs. The Rigoletto project focuses on creating a RISC-V automotive hardware platform, supporting the development of an open-source, software-defined vehicle ecosystem.

The candidate will work remotely within a European context, with residency in Italy, France, Spain, Belgium, Portugal, or Germany.

Responsibilities:

• Develop and extend testbenches using SystemVerilog and UVM, verifying IPs with random instructions
• Utilize GitHub for open-source integration and maintenance under core-v-verif
• Verify CPUs, ISA extensions, peripherals, cache-coherency, and dual-core systems based on RISC-V
• Support and extend existing CPU designs to support additional features
• Engage with the OpenHW Technical Working Group to promote participation and adoption
• Support the broader objectives of the Eclipse Foundation’s European research initiatives, including dissemination, community-building, and representation at events

Qualifications:

• Bachelor’s degree or higher in EE or CS with 5+ years of experience
• Fluent in English (spoken and written)
• Proficiency with SystemVerilog, UVM, Linux, Make, and Python
• Knowledge of computer architectures, peripherals, bus protocols, interrupt controllers, MMUs, caches, and multicore systems
• Familiarity with RISC-V specifications, formal verification, RTL design, and Git is a plus

We offer competitive compensation and a comprehensive benefits package. We are committed to diversity and inclusion, providing accommodations for applicants with disabilities during the recruitment process.