ASIC Analog Designer (f/m/div.)

Sei unter den ersten Bewerbenden.
Nur für registrierte Mitglieder
Kusterdingen
EUR 70.000 - 100.000
Sei unter den ersten Bewerbenden.
Vor 3 Tagen
Jobbeschreibung

Job Description

Join Bosch in shaping beneficial technologies across various sectors including mobility solutions, consumer goods, industrial technology, energy, and building technology. Contribute to improving quality of life globally at our Kusterdingen ASIC development center, where we develop ASICs for consumer applications.

Responsibilities include:

  1. Shaping the future: Engage in leading-edge development projects for MEMS consumer sensor ASICs, contributing to system architecture and block-level analog circuit design for next-generation sensors.
  2. Implementation: Develop challenging blocks and mixed-signal sensor systems suitable for high-volume production.
  3. Coordination: Understand design requirements, derive top-level architecture, specify blocks, and support layout and testing programs.
  4. Evaluation: Responsible for product validation, including characterization and qualification assessments.

Candidate Profile:

  • Enthusiastic, creative, and willing to work in international, interdisciplinary teams.
  • Team player with a quality-oriented and independent working style.
  • Minimum 5 years of experience in Analog IC design, preferably with system-level architecture of sensor frontends in CMOS technology.
  • Proficient with state-of-the-art EDA software tools for IC design and modeling.
  • Fluent in English; German language skills are beneficial.
  • Educational qualification: MSc. or PhD in Electrical Engineering, Computer Science, Mathematics, or a comparable field.

Additional Benefits:

  • Flexible work arrangements for work-life balance.
  • Health and sports activities.
  • Childcare services.
  • Employee discounts.
  • Creative work environment.
  • In-house social counseling and care services.

The recruitment contact or supervisor will provide information about the individual benefit plan.