Digital IC Verification Engineer | UVM/SystemVerilog Expert

A leading company in power electronics based in Emilia-Romagna is seeking a UVM Verification Engineer to join their growing team. Responsibilities include developing test plans and building reusable verification models. Ideal candidates will have strong knowledge of HDL, experience in scripting languages like Tcl and Python, and familiarity with ASIC design flow. Competitive salary and opportunities for growth are offered.