Principal Analog Design Engineer

Overview

Principal Analog Design Engineer

Pavia, Italy €85,000 to €110,000 + Bonus + SIGNING BONUS + Paid Relocation

This role is a key position within our Optical PHY (CE-OPHY) team, which is part of our Central Engineering division. Our team designs high-speed and optical transceivers for modern communication infrastructure to address the bandwidth demand in mega data centers powering social media, video-on-demand, gaming, and other real-time data streams. We develop innovative, first-to-market chips and subsystem solutions that push data rates and power efficiency.

Key Responsibilities

• Design & Architecture: Analyze and interpret block specifications, own transistor-level design, and select appropriate topologies. Design entire analog macros or IPs from concept to mass production.
• Verification & Validation: Model and validate circuit blocks. Supervise and guide layout activities, provide clear guidelines, and conduct post-layout verifications to ensure design integrity.
• Collaboration & Leadership: Work closely with other engineering teams to enhance solutions and participate in cross-functional meetings. Train and mentor junior designers to build the team\'s expertise.
• Project Management: Manage pre-silicon tasks (simulation and modeling) and post-silicon tasks (lab characterization, debugging, correlating measurements to simulations) through to high-volume production.

Candidate Profile

We are seeking a seasoned engineer with a deep background in analog IC design and a passion for pushing technological limits.

• Education & Experience: A Master\'s degree or Ph.D. in Electrical Engineering or a related field is required, with 12-15 years of professional experience.
• Technical Skills: Proven experience in designing ICs from architecture definition through lab characterization and volume production. Strong experience in analog design, preferably in the multi-GHz range. Proficiency in supervising custom analog layout, using standard EDA CAD tools, and debugging designs to correlate simulations with measurements.
• Preferred Qualifications: Experience with multi-Gbps electrical SerDes or electro-optical transceivers is highly desirable. Knowledge of advanced CMOS nodes, including FinFET, is advantageous.
• Personal Skills: Strong communication, presentation, and documentation skills. Proficiency in both written and spoken Italian and English (minimum B2 level).
• Work Model: This is an on-site, full-time position located in Pavia, Italy.