Sr. ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team
Sr. ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team
Utility Computing (UC) provides product innovations—from foundational services such as Amazon’s Simple Storage Service (S3) and Amazon Elastic Compute Cloud (EC2) to consistently released new product innovations that continue to set AWS’s services and features apart in the industry. As a member of the UC organization, you’ll support the development and management of Compute, Database, Storage, Internet of Things (Iot), Platform, and Productivity Apps services in AWS, including support for customers who require specialized security solutions for their cloud services.
Annapurna Labs (our organization within AWS UC) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.
About AWS
Amazon Web Services (AWS) is the world’s most comprehensive and broadly adopted cloud platform. We pioneered cloud computing and never stopped innovating — that’s why customers from the most successful startups to Global 500 companies trust our robust suite of products and services to power their businesses.
Key responsibilities
- Integrate multiple subsystems into top-level SOC; ensure correct clock/reset/functional/DFT signal routing.
- Implement and deliver high‑performance, area and power‑efficient RTL to achieve design targets and specifications.
- Analyze design, microarchitecture or architecture to make trade‑offs based on features, power, performance or area requirements.
- Develop micro‑architecture, implement SystemVerilog RTL, and deliver synthesis/timing‑clean design with constraints.
- Perform lint and clock domain crossing quality checks on the design.
- Work with architects, other designers, verification teams, pre‑ and post‑silicon validation teams, synthesis, timing and back‑end teams to accomplish tasks.
Basic Qualifications
- B.S. in Electrical Engineering or related technical field.
- 5+ years in RTL design for SOC.
- 5+ years of VLSI engineering.
- 5+ years with code quality tools including Spyglass, LINT, or CDC.
Preferred Qualifications
- Master’s degree in electrical engineering, computer engineering, or equivalent.
- Experience with Microarchitecture, SystemVerilog RTL, Assertions, SDC constraints.
- Experience with automation and scripting languages such as Python.
- Familiarity with data path design, interconnects, AXI protocol.
- Good analytical, problem solving, and communication skills.
Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records.
Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.
Posted: December 17, 2025 (Updated 1 day ago)