Principal Analog Design Engineer.

Overview

Principal Analog Design Engineer

Pavia, Italy €85,000 to €110,000 + Bonus + SIGNING BONUS + Paid Relocation

This role is a key position within our Optical PHY (CE-OPHY) team, which is part of our Central Engineering division. Our team is at the forefront of designing high-speed and optical transceivers for modern communication infrastructure. This technology is critical for addressing the explosive demand for bandwidth in mega data centers that power social media, video-on-demand, gaming, and other real-time data streams. We are dedicated to developing innovative, first-to-market chips and subsystem solutions that push the boundaries of data rates and power efficiency.

Key Responsibilities

• Design & Architecture: Analyze and interpret block specifications, taking ownership of transistor-level design and selecting the most appropriate topologies. Design entire analog macros or IPs from initial concept to final mass production.
• Verification & Validation: Model and validate circuit blocks. Supervise and guide layout activities, provide clear guidelines, and conduct rigorous post-layout verifications to ensure design integrity.
• Collaboration & Leadership: Work closely with other engineering teams to enhance existing solutions and participate in cross-functional meetings. Train and mentor junior designers to build the team\'s collective expertise and technical strength.
• Project Management: Manage pre-silicon tasks such as simulation and modeling, and post-silicon tasks including lab characterization, debugging, and correlating measurements to simulations, up to high-volume production.

Candidate Profile

We are seeking a seasoned engineer with a deep background in analog IC design and a passion for pushing technological limits.

Education & Experience

A Master\'s degree or Ph.D. in Electrical Engineering or a related field is required, along with 12-15 years of professional experience.

Technical Skills

You must have proven experience in designing ICs from the architecture definition phase through to lab characterization and volume production. Solid experience in analog design, preferably in the multi-GHz range, is essential. Proficiency in supervising custom analog layout, using standard EDA CAD tools, and debugging designs to correlate simulations with measurements is required.

Preferred Qualifications

Experience with multi-Gbps electrical SerDes or electro-optical transceivers is highly desirable. Knowledge of advanced CMOS nodes, including FinFET, would be a significant advantage.

Personal Skills

Strong communication, presentation, and documentation skills. Proficiency in both written and spoken Italian and English (minimum B2 level) is required due to our international team and location.

Work Model

This is an on-site, full-time position located in Pavia, Italy.