Verification Engineer

Solo per membri registrati
Assago
EUR 40.000 - 55.000
Descrizione del lavoro

Come join Analog Devices (ADI) – a place where Innovation meets Impact. For more than 55 years, Analog Devices has been inventing new breakthrough technologies that transform lives. At ADI you will work alongside the brightest minds to collaborate on solving complex problems that matter from autonomous vehicles, drones and factories to augmented reality and remote healthcare.

ADI fosters a culture that focuses on employees through beneficial programs, aligned goals, continuous learning opportunities, and practices that create a more sustainable future.

About Analog Devices

Analog Devices, Inc. (NASDAQ : ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more atand onand.

Verification Engineer

Job Description :

We are seeking a motivated, Verification Engineer to provide support to our Industrial Multi Markets-Industrial Automation Business Unit located at ADI's Milan.

The candidate will be self-motivated and will join a team of experienced Digital designers and work effectively within a group of Analog designers, Layout Designers, Test Engineers, and Application Engineers. The candidate will be involved from the definition, through the development till test and customer support of Industrial Automation products.

Responsibilities and Duties include but not limited to :

  • Verification of complex chips and sub-systems using leadingedge verification methodologies required to implement new products
  • Development of directed and constrained random scenarios in System Verilog UVM
  • Development of Formal Verification checks
  • Architect, implement, and manage complete metric-driven System Verilog and UVM verification environments as determined by project complexity combining DMS and AMS, Top-Level and IP-Level
  • Create verification plans for blocks and full chip by developing a thorough understanding of the design under test. Keep track of the verification status and manage resources to match the design schedule.
  • Support post-silicon validation activities of the products working with design, applications, and test teams
  • Gate level simulations and debug of digital blocks and full-chip
  • Develop behavioral models for analog and mixed-signals blocks

Minimum Qualifications :

  • Degree in Electrical Engineering, Computer Science, Computer Engineering or VLSI Design
  • Excellent debug capabilities and problem-solving skills
  • Team working attitude across multi-discipline. Strong communication skills
  • Proficient in object-oriented programming, scripting and automation with TCL or Python.
  • Committed to further learning, with a passion to develop a career in the semiconductor Industry
  • Basic Knowledge of SW development flows.
  • Excellent written and verbal communication (both Italian and English)

    • Preferred Qualifications :

  • Knowledge of Verilog, System Verilog and UVM
  • Knowledge of Assertions languages (PSL and / or SVA)
  • Basic knowledge of Revisioning tools such as SubVersion, CVS and Git.
  • Basic knowledge of Bug Tracking tools like Bugzilla and Jira.
  • Continuous Integration tools are a plus.
  • Basic knowledge of Analog Circuit Design and / or Digital Design is nice to have.

    • Job Req Type : Graduate JobRequired Travel : Yes, 10% of the time