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Mixed-Signal Verification Engineer (SystemVerilog/UVM)

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Livorno
EUR 50.000 - 70.000
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Ieri
Descrizione del lavoro
A leading technology company is seeking an experienced engineer to join their Analog Mixed Signal Design Verification Team. The role involves developing verification test plans, designing test benches, and collaborating with various teams to ensure compliance with system requirements. Candidates should have a Master’s in Electrical Engineering and hands-on experience with mixed signal verification tools. This position is full-time based in Livorno, Italy.