Principal Digital Verification Engineer

Role Overview

As a Principal Digital Verification Engineer, you will lead the pre‑silicon verification of complex IP blocks, subsystems, or SoCs for automotive and industrial applications, with a strong focus on electrification solutions. In addition to defining verification strategies and developing advanced test environments, you will coordinate and mentor a team of verification engineers, ensuring alignment with project goals and best practices.

Key Responsibilities

• Define and execute comprehensive verification plans aligned with design specifications and industry standards.
• Develop, maintain, and debug UVM/SystemVerilog‑based testbenches for RTL, gate‑level, and power‑aware simulations.
• Create and manage test cases, assertions (SVA/PSL), monitors, and coverage metrics (code and functional).
• Lead and coordinate a team of verification engineers, providing technical guidance, task planning, and performance feedback.
• Drive methodology improvements and adoption of best practices, including formal verification techniques and automatic code and report generation.
• Collaborate cross‑functionally with hardware, firmware, and system architecture teams to ensure design quality and integration.
• Support post‑silicon validation and debug, correlating RTL and silicon behavior.

Preferred Skills

• Familiarity with automotive and industrial domains, especially electrification systems.
• Hands‑on experience with EDA tools (Cadence Xcelium, JasperGold, VManager).
• Knowledge of standard protocols (SPI, I2C, UART, APB).
• Hands‑on experience with Python, Makefile, Tcl, shell languages.
• Continuous learning mindset and ability to drive innovation in verification methodologies.

Seniority Level

Mid‑Senior level

Employment Type

Full‑time

Industries

Semiconductor Manufacturing

Location

Nova Milanese, Lombardy, Italy