Staff Hardware Design Engineer — NoC & SoC Architect

Arteris; Kraków; On-site; PLN 180,000 - 300,000; Full time

Job summary

Arteris is seeking a Staff Hardware Design Engineer in Kraków, Poland to design and develop advanced hardware blocks for configurable NoC IP products. You will be a senior technical contributor shaping architecture, RTL coding, verification, and optimization.

Bring 8–12 years of SoC/IP/NoC experience, deep knowledge of coherent and non-coherent protocols (AMBA/AXI/PCIe), CPU architectures (ARM/RISC-V), and strong Verilog/SystemVerilog skills.

Qualifications

• 8–12 years of experience in SoC/IP/NoC design.
• Expertise with coherent and non-coherent protocols (AMBA, AXI, PCIe, CXL, CHI).
• Strong understanding of ARM/RISC-V CPUs, caches and memory coherence.
• Proficiency in Verilog/SystemVerilog and EDA tools.

Responsibilities

• Design and develop complex hardware blocks for configurable IPs, including RTL coding and performance optimization.
• Define architecture specifications for NoC components and propose improvements.
• Develop verification environments and define functional coverage strategies.
• Collaborate with hardware, software, and verification teams to ensure cohesive integration.
• Document designs and mentor less experienced engineers.

Skills

SoC/IP/NoC design

ARM/RISC-V CPU architectures

Verilog/SystemVerilog

C/C++/Python scripting

Memory coherence concepts

English fluent

Education

Master's degree in electrical engineering or computer science

Tools

Cadence

Synopsys

Mentor Graphics

Job description

Arteris is seeking a Staff Hardware Design Engineer in Kraków, Poland to design and develop advanced hardware blocks for configurable NoC IP products. You will be a senior technical contributor shaping architecture, RTL coding, verification, and optimization.

Bring 8–12 years of SoC/IP/NoC experience, deep knowledge of coherent and non-coherent protocols (AMBA/AXI/PCIe), CPU architectures (ARM/RISC-V), and strong Verilog/SystemVerilog skills.