Senior SoC Verification Engineer - UVM, SystemVerilog

Elektro; Katowice; On-site; PLN 180,000 - 240,000; Full time

Job summary

A leading technology company based in Katowice is seeking a Senior Verification Engineer to join their SoC Verification team. The role involves developing System Verilog UVM testbenches, implementing functional coverage models, and ensuring complete design verification. Candidates should have strong proficiency in System Verilog, extensive experience with simulation tools, and excellent communication skills. This position offers various perks, including sharing the costs of sports activities and private medical care.

Benefits

Sharing the costs of sports activities

Private medical care

Sharing the costs of foreign language classes

Qualifications

• 5+ years or equivalent of relevant experience in SoC verification.
• Good understanding of assertion-based verification methodologies.
• Hands on experience using industry standard simulation & debugging tools.

Responsibilities

• Develop System Verilog UVM testbenches and resolve complex test bench challenges.
• Define and implement a functional coverage model.
• Develop a deep understanding of complex SoCs and IPs.

Skills

System Verilog

UVM

Python

Problem-solving skills

C / C++

Education

Bachelor’s degree in Computer Science, Engineering or related field

Tools

Questa

VCS

Verdi

Jenkins

GIT

Job description

A leading technology company based in Katowice is seeking a Senior Verification Engineer to join their SoC Verification team. The role involves developing System Verilog UVM testbenches, implementing functional coverage models, and ensuring complete design verification. Candidates should have strong proficiency in System Verilog, extensive experience with simulation tools, and excellent communication skills. This position offers various perks, including sharing the costs of sports activities and private medical care.