PD Partition Lead (Physical Design, Semiconductors)

Capgemini; Polska; Hybrid; PLN 180.000 - 300.000; Vollzeit

Benefits dieser Stelle

Medicover medical care

Private life insurance

Sports card

75+ training tracks on NEXT platform

Zusammenfassung

Capgemini Polska is seeking a Physical Design Partitioning Lead to drive all PD activities for advanced node projects. You will lead planning, timing closure, and sign-off, while mentoring junior engineers.

The role emphasizes deep floorplanning, power mesh, clock tree, and ECO generation. Hybrid work model and strong governance support are provided.

Qualifikationen

• Strong knowledge of synthesis flow, insertDFT scan/coverage and optimization.
• Excellent floorplan, power plan, CTS, place, route, and timing closure skills.
• Proficiency using Perl/TCL/Python scripting and Makefile.
• Expertise in timing STA/PTSI – signal integrity closure, ECO generation/implementation.
• Excellent EM/IR, DRC, LVS, ERC analysis and fixing skills.
• Experience with sign-off tape-out closure work.
• Partitioning experience is a plus.
• Experience in leading/tech leading small teams is a plus.

Aufgaben

• Responsible for all aspects of Physical Design in full chip or block level in advanced technologies nodes (10nm and below).
• Deep Floorplanning, partitioning/budgeting, power mesh distribution, clock tree planning and analysis, Scan re-ordering, placement, CTS, place and route.
• Cover timing analysis and ECO tasks; sign-off closure including SI/noise.
• Handle validation/qualification tasks: Formal Verification, EM/IR, DRC, LVS, Antenna, ERC.
• Contribute to Low Power solution development and implementation.
• Develop/enhance timing-related scripts for clock skew analysis and critical path analysis.
• Lead small PD engineer teams as needed.

Kenntnisse

Synthesis flow

Floorplan

CTS

Timing closure

Scripting (Perl/TCL/Python)

EM/IR/DRC/LVS/ERC analysis

Sign-off tape-out

Partitioning experience

Team leadership

Tools

Makefile

Perl

TCL

Python

Jobbeschreibung

At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same.## **Your role**Are you in search for a new challenge? We are looking for Physical Design expert with experience in partitioning who dreams about becoming a Lead or Tech Lead for new, exciting projects! Take the opportunity and join us as a **PD Partitioning Lead!**## **Your tasks*** Responsible for all aspects of Physical Design in full chip or block level in extremely advanced technologies nodes (10nm and below);* In deep Floorplanning, partitioning/budgeting, power mesh distribution, clock tree planning and analysis, Scan re-ordering, placement, CTS, place and route;* Cover all relevant activities related to timing analysis (closure through sign-off including SI/noise) ECO tasks (both functional and timing);* In charge with all validation/qualification tasks: Formal Verification, EM/IR, DRC, LVS, Antenna, ERC analysis and fixes;* Be part of the overall Low Power solution development and implementation;* Develop/enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from top-level to block level);* Complete multiple design cycles of high complexity with little supervision.* Possiblity to lead other PD Engineers.## **Your profile*** Good knowledge of synthesis flow, insertDFT scan/coverage and optimization;* Excellent floorplan, power plan, CTS, place, route, and timing closure skills;* Proficiency using Perl/TCL/Python scripting and Makefile;* Expertise in timing STA/PTSI – signal integrity closure, ECO generation/implementation skill;* Excellent EM/IR, DRC, LVS, ERC analysis and fixing skills;* Experience with sign-off tape-out closure work;* Partitioning experience is a plus;* Experience in leading/tech leading small teams will be a plus.## **What You'll love about working here*** **Well-being culture:**medical care with Medicover, private life insurance, and sports card. But we went one step further by creating our own Capgemini Helpline offering therapeutical support if needed and the educational podcast 'Let's talk about wellbeing' which you can listen to on Spotify.* **Access to over 70 training tracks** with certification opportunities (e.g., GenAI, Architects, Google) on our NEXT platform. Dive into a world of knowledge with free access to Education First languages platform, TED Talks and Udemy Business materials and trainings.* **Continuous feedback and ongoing performance discussions** thanks to our performance management tool GetSuccess supported by a transparent performance management policy.* **Enjoy hybrid working model** that fits your life - after completing onboarding, connect work from a modern office with ergonomic work from home, thanks to home office package (including laptop, monitor, and chair). Ask your recruiter about the details.## **Get to know us**Capgemini is committed to diversity and inclusion, ensuring fairness in all employment practices. We evaluate individuals based on qualifications and performance, not personal characteristics, striving to create a workplace where everyone can succeed and feel valued.Do you want to get to know us better? Check our Instagram — @capgeminipl or visit our Facebook profile — Capgemini Polska. You can also find us on YouTube.