Senior Digital Design Engineer – RTL, DV & Mixed-Signal

Analog Devices, Inc.; Taguig; On-site; PHP 600,000 - 1,200,000; Full time

Job summary

Analog Devices, Inc. in the Philippines seeks a Digital Design Engineer to contribute to RTL design, subsystem implementation, and mixed-signal integration under senior guidance.

The role spans RTL creation, verification collaboration, and supporting implementation flows while developing digital verification skills. The candidate will work with DV engineers for coverage closure, assist in UVM components, and coordinate with AMS and physical design teams in a fast-paced environment.

Qualifications

• BS or MS in ECE, EE, CpE, or equivalent.
• 2–5 years digital design experience, or strong NCG background.
• Proficiency in SystemVerilog/Verilog; familiarity with UVM preferred.
• Experience with scripting languages (Python/Perl/TCL).
• Basic understanding of AMS modeling and mixed-signal flows is a plus.
• Strong analytical, problemsolving, and communication skills.
• Capable of performing independent research and self study

Responsibilities

• Write RTL for digital blocks based on specifications.
• Perform lint, CDC analysis, and support DFT integration.
• Assist in writing functional testcases and simple UVM components.
• Collaborate with DV engineers for coverage closure and bug resolution.
• Support AMS co-simulation and integration with analog blocks.
• Work with physical design teams on synthesis and timing.
• Train and develop skills in digital design verification

Skills

SystemVerilog/Verilog

Python/Perl/TCL

Analytical skills

Communication skills

Independent research

Education

BS or MS in ECE, EE, CpE, or equivalent

Tools

UVM

Job description

Analog Devices, Inc. in the Philippines seeks a Digital Design Engineer to contribute to RTL design, subsystem implementation, and mixed-signal integration under senior guidance.

The role spans RTL creation, verification collaboration, and supporting implementation flows while developing digital verification skills. The candidate will work with DV engineers for coverage closure, assist in UVM components, and coordinate with AMS and physical design teams in a fast-paced environment.