Senior ASIC Verification Engineer — Clocks & Resets (Hybrid)

NVIDIA Corporation; Hinoba-an; Hybrid; PHP 1,000,000 - 1,400,000; Full time

Benefits offered by this job

Hybrid work model

Job summary

NVIDIA Corporation is seeking a Senior ASIC Verification engineer to validate clocking structures for Tegra automotive and datacenter products from start to finish. You will develop test plans, automate validation, and ensure bug-free clocking and reset logic across platforms.

The role requires 2+ years in verification, strong SystemVerilog/UVM skills, and proficiency in C++ and Python, with collaboration across multiple groups and time zones. Hybrid work model applies.

Qualifications

• BS or MS in EE/ECE or equivalent experience.
• 2+ years of relevant industry work experience.
• Strong understanding of logic design and architecture.
• Expertise in SV constraint random verification, UVM, formal verification, coverage metrics, profiling tools.
• Exposure to block-level and system-level verification.
• Strong coding in SystemVerilog, scripting languages (Perl/Python) and C++.
• Ability to collaborate across groups and handle pre-silicon test plans.

Responsibilities

• Own validation of clocking structures from start to finish, including test plan development and coverage metrics.
• Develop automation and validation flows, execute tests, identify and fix bugs, and productize results.
• Tackle sophisticated problems and develop scalable cross-platform solutions.
• Hands-on with industry-standard verification tools and NVIDIA-specific compilers and tools.
• Coordinate with internal and external teams across time zones.

Skills

SystemVerilog

UVM

C++

Python

Perl

Test plan development

Education

BS in EE/ECE

MS in EE/ECE

Tools

Verilog/SystemVerilog tooling

Formal Verification

Job description

NVIDIA Corporation is seeking a Senior ASIC Verification engineer to validate clocking structures for Tegra automotive and datacenter products from start to finish. You will develop test plans, automate validation, and ensure bug-free clocking and reset logic across platforms.

The role requires 2+ years in verification, strong SystemVerilog/UVM skills, and proficiency in C++ and Python, with collaboration across multiple groups and time zones. Hybrid work model applies.