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NVIDIA Corporation is seeking a Senior ASIC Verification engineer to validate clocking structures for Tegra automotive and datacenter products from start to finish. You will develop test plans, automate validation, and ensure bug-free clocking and reset logic across platforms.
The role requires 2+ years in verification, strong SystemVerilog/UVM skills, and proficiency in C++ and Python, with collaboration across multiple groups and time zones. Hybrid work model applies.
The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification. The NVIDIA Clocks Team is committed to deliver high-quality clocking and reset logic to various units in SOC automotive and datacenter ASICs. The complexity of the clocks and resets design has increased many folds. This requires sophisticated verification to deliver a bug free clocks/resets design to power our product lines ranging from Data Centers, Consumer graphics to Self-driving cars and the growing field of artificial intelligence. Modern clocking verification solutions need to be innovative, ensure quality in covering the complex design specifications and balance the constraints on infrastructure, re-usability, testing speed and multi-platform support.
We have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our world-class engineering teams are growing fast.
If you are creative, curious, and motivated with real passion for technology, we want to hear from you!
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