Senior ASIC/FPGA Implementation Lead - RTL & Timing

Xinyx Design Consultancy & Services, Inc.; Muntinlupa; Presencial; PHP 800.000 - 1.500.000; Jornada completa

Descripción de la vacante

Xinyx Design Consultancy & Services, Inc. in Metro Manila seeks a Senior Digital Implementation Engineer to lead end-to-end ASIC/FPGA implementation, including synthesis, place-and-route, and timing closure.

The role requires strong RTL/Verilog skills and hands-on experience with major EDA flows. You will mentor junior engineers and collaborate with RTL, verification, and physical design teams to ensure design intent and timing goals are met, delivering robust blocks on aggressive schedules.

Formación

• Strong RTL/Verilog skills required.
• Hands-on experience with major EDA flows.

Responsabilidades

• Lead end-to-end ASIC/FPGA implementation, including synthesis, place-and-route, and timing closure.
• Mentor junior engineers and review design quality.
• Collaborate with RTL, verification and physical design teams to ensure timing goals.

Conocimientos

RTL/Verilog

Synthesis

Place-and-Route

Timing Closure

Herramientas

EDA tools

Descripción del empleo

Xinyx Design Consultancy & Services, Inc. in Metro Manila seeks a Senior Digital Implementation Engineer to lead end-to-end ASIC/FPGA implementation, including synthesis, place-and-route, and timing closure.

The role requires strong RTL/Verilog skills and hands-on experience with major EDA flows. You will mentor junior engineers and collaborate with RTL, verification, and physical design teams to ensure design intent and timing goals are met, delivering robust blocks on aggressive schedules.