Entry-Level Design Verification Engineer - Growth & Mentorship

Hammerjack Pty Ltd; Philippines; On-site; PHP 300,000 - 420,000; Full time

Job summary

Analog Devices is seeking an Associate Design Verification Engineer to develop basic test benches and verify new digital, analog, and mixed-signal products before tape-out. This entry-level role emphasizes learning under supervision and growing technical skills in verification methodologies.

You will gain hands-on experience with SystemVerilog/UVM, scripts, and debugging while collaborating with experienced engineers to shape the future of innovative semiconductor solutions.

Qualifications

• SystemVerilog and UVM knowledge for basic test benches and verification

Responsibilities

• Develop and execute basic test benches for mixed-signal product verification
• Create and maintain basic test environments using SystemVerilog/UVM
• Conduct code coverage analysis to ensure design accuracy
• Debug simulation failures and track coverage metrics
• Support verification planning and documentation
• Collaborate with design teams to understand requirements
• Identify potential design issues under guidance of senior team members
• Document verification processes and results

Skills

SystemVerilog/UVM

Python/Perl/TCL

Verilog RTL

Digital Interfaces (I2C/SPI/UART)

Simulation Tools

Problem Solving

Communication

Education

Bachelor's degree in Electrical/ Electronics/Computer Engineering or related

Job description

Analog Devices is seeking an Associate Design Verification Engineer to develop basic test benches and verify new digital, analog, and mixed-signal products before tape-out. This entry-level role emphasizes learning under supervision and growing technical skills in verification methodologies.

You will gain hands-on experience with SystemVerilog/UVM, scripts, and debugging while collaborating with experienced engineers to shape the future of innovative semiconductor solutions.