Sr. Engineer, Verifications

Qabird; Rijswijk; On-site; EUR 65,000 - 85,000; Full time

Benefits offered by this job

Base salary

Bonus based on goals

Equity options

Job summary

Qabird is seeking a Senior Verification Engineer for their Rijswijk office. You will develop MEMS timing ICs, focusing on both analog and mixed-signal environments. Ideal candidates possess strong expertise in SystemVerilog, UVM methodologies, and have extensive experience in semiconductor verification.

The role includes developing verification plans, running simulations, and engaging with stakeholders to ensure efficient workflows.

Qualifications

• 5+ years of verification experience in the semiconductor industry.
• Proficient in verification using UVM.
• Strong experience writing SystemVerilog Assertions (SVA).

Responsibilities

• Develop SV-RNM models for analog and mixed-signal circuits.
• Develop UVM-based verification environment.
• Run simulations and debug results.

Skills

SystemVerilog

UVM

Scripting languages (Perl/Python)

Verilog

Analog schematic understanding

C++

Education

MS (BS) degree in electrical/computer engineering or related fields

Tools

Cadence Virtuoso

Job description

About SiTime

SiTime Corporation is the precision timing company. Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power and better reliability. With more than 3 billion devices shipped, SiTime is changing the timing industry. For more information, visit www.sitime.com.

Job Summary

As a Senior Verification Engineer, you will be part of a team developing MEMS timing ICs. It is not necessary to meet all job requirements to be a qualified candidate for the position.

Responsibilities

• Developing SV-RNM models for both analog and mixed-signal circuits
• Developing verification plan from chip or block specifications
• Developing UVM-based verification environment (scoreboards, monitors, sequencers, etc.)
• Developing digital-top verification in System Verilog
• Defining and writing System Verilog Assertions (SVA)
• Defining and writing functional coverages and covergroups
• Running simulations and debugging simulation results
• Reviewing verification results for Tape‑out sign‑off
• Communicating with stakeholders (design/test/verification) to facilitate teamwork and efficient sharing of information and exchange of ideas

Minimum Requirements

• MS (BS) degree in electrical/computer engineering or related fields with 5 (8) years of work experience doing verification in the semiconductor industry
• Good verbal and written communication skills in English
• Proficient in SystemVerilog and SystemVerilog OOP
• Fluency in utilizing scripting languages such as Perl / Python
• Proficient in verification using UVM
• Strong experience writing SystemVerilog Assertions (SVA)
• Understanding of analog schematic and experience with Cadence Virtuoso
• Basic understanding of digital design using Verilog
• Ability to communicate and work effectively with geographically dispersed teams of mixed‑signal, digital design and analog design engineers
• Ability to work independently and drive solutions to challenging problems

Desired Qualification

• Experience with generating functional models for analog blocks using SystemVerilog RNM, Wreal (V‑AMS), or similar techniques
• Experience with UVM‑AMS methodology
• Solid experience with Formal Property Verification (FPV)
• Programming experience writing OOP code in C++
• Excellent written and verbal communication skills in English
• Experience with performing analog mixed‑signal verification
• Proven track record in working well with others in fast‑paced and collaborative work environment
• Knowledge of analog design
• Knowledge of synthesizable digital design
• Experience working on verification of datapath designs including filters

Compensation

The actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors.

SiTime compensation packages includes base salary, bonus based on achieving your innovation goals and equity.

Equal Opportunity Employer

SiTime is an Equal Opportunity Employer. We treat each person fairly and we do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, or marital status or other characteristics protected by law. SiTime participates in the E‑Verify program.