Sr. Engineer, Verifications

SiTime; Rijswijk; On-site; EUR 70,000 - 90,000; Full time

Job summary

A technology company is seeking a Sr. Engineer, Verifications to develop MEMS timing ICs. The successful candidate will have substantial experience in verification, preferably in the semiconductor industry, and be skilled in SystemVerilog and UVM. This role involves developing verification models and communicating with cross-functional teams to ensure quality and innovation. Competitive compensation and bonuses are offered.

Qualifications

• 5 years experience in verification in the semiconductor industry.
• Good communication skills in English.
• Proficient in SystemVerilog and OOP.

Responsibilities

• Develop SV-RNM models for analog and mixed-signal circuits.
• Create verification plans from specifications.
• Run simulations and debug results.

Skills

SystemVerilog

Scripting languages (Perl/Python)

UVM verification

SystemVerilog Assertions (SVA)

Cadence Virtuoso

Digital design understanding (Verilog)

Communication skills

Education

MS degree in electrical/computer engineering

Job description

Overview

Sr. Engineer, Verifications role at SiTime. As a Senor Verification Engineer, you will be part of a team developing MEMS timing ICs.

It is not necessary to meet all job requirements to be a qualified candidate for the position.

Responsibilities

• Developing SV-RNM models for both analog and mixed-signal circuits
• Developing verification plan from chip or block specifications
• Developing UVM-based verification environment (scoreboards, monitors, sequencers, etc.)
• Developing digital-top verification in System Verilog
• Defining and writing System Verilog Assertions (SVA)
• Defining and writing functional coverages and covergroups
• Running simulations and debugging simulation results
• Reviewing verification results for Tape-out sign-off
• Communicating with stakeholders (design/test/verification) to facilitate teamwork and information exchange

Qualifications

Minimum Requirements:

• MS (BS) degree in electrical/computer engineering or related fields with 5 (8) years of work experience doing verification in the semiconductor industry
• Good verbal and written communication skills in English
• Proficient in SystemVerilog and SystemVerilog OOP
• Fluency in scripting languages such as Perl / Python
• Proficient (through work experience) in verification using UVM
• Strong experience writing SystemVerilog Assertions (SVA)
• Understanding of Analog schematic and experience with Cadence Virtuoso
• Basic understanding of digital design using Verilog
• Ability to communicate and work effectively with geographically dispersed teams of mixed-signal, digital design and analog design engineers
• Ability to work independently and drive solutions to challenging problems

Desired Qualification:

• Experience with generating functional models for analog blocks using SystemVerilog RNM, Wreal (V-AMS), or similar techniques
• Experience with UVM-AMS methodology
• Solid experience with Formal Property Verification (FPV)
• Programming experience writing OOP code in C++
• Excellent written and verbal communication skills in English
• Experience with performing analog mixed-signal verification
• Proven track record in working well with others in fast-paced and collaborative work environment
• Knowledge of analog design
• Knowledge of synthesizable digital design
• Experience working on verification of datapath designs including filters

Compensation and Legal

The actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors. SiTime compensation packages include base salary, bonus based on achieving your innovation goals and equity.

SiTime is an Equal Opportunity Employer. We treat each person fairly and we do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, or marital status or other characteristics protected by law. SiTime participates in the E-Verify program.

Learn More about SiTime: Review the Get to Know SiTime section of our career page to explore our culture, values, and what makes us unique.