Senior Digital IC Design Engineer (Hybrid)

StarIC Inc; Utrecht; Hybrid; EUR 75,000 - 95,000; Full time

Benefits offered by this job

Competitive pay

Great work environment

Hybrid work arrangement

IC tape-out experience

Job summary

StarIC Inc. is seeking a Digital Design Engineer to lead digital development projects for mixed-signal ICs. You will own digital blocks from concept through verification and work with global teams across frontend and backend flows.

Ideal candidates have 3–6 years in digital IC design, strong VHDL/Verilog skills, and experience with Synopsys/Cadence Mentor tools. Hybrid work options are available, with a dynamic, learning-driven culture and global client engagements.

Qualifications

• BSc or MSc in Electronic Engineering or Computer Engineering is required.
• 3–6 years of digital IC design experience (academic work considered).
• Experience with VHDL and/or Verilog design and simulation.
• Front-End tools experience (Synopsys, Cadence or Mentor’s) including verification, simulators, synthesis, STA and gate-level simulation.

Responsibilities

• Lead and manage digital development and design projects.
• Own all phases of digital blocks and ICs development from concept to final verification.
• Oversee design cycle activities: spec, modeling, RTL, verification, synthesis, timing, tests, layout support and documentation.
• Plan and execute updates to existing digital designs and supporting software.
• Lead design reviews and support backend design targeting silicon, FPGAs, and system simulators.

Skills

Digital IC design

Scripting (csh Tcl Perl)

English communication

Project management

Education

BSc or MSc in Electronic/Computer Engineering

Tools

VHDL

Verilog

Synopsys/Cadence/Mentor tools

Synthesis/STA tooling

Lab/verification workflows

Job description

StarIC Inc. is seeking a Digital Design Engineer to lead digital development projects for mixed-signal ICs. You will own digital blocks from concept through verification and work with global teams across frontend and backend flows.

Ideal candidates have 3–6 years in digital IC design, strong VHDL/Verilog skills, and experience with Synopsys/Cadence Mentor tools. Hybrid work options are available, with a dynamic, learning-driven culture and global client engagements.