Lead Logic Design Engineer — Secure Silicon IP

Rambus; Vught; Hybrid; EUR 120,000 - 160,000; Full time

Job summary

Rambus, a premier chip and silicon IP provider, seeks a Lead Member of Technical Staff Logic Design Engineer to join our Silicon IP team in Vught. The role involves leading digital design for secure IPs, coordinating with verification, architecture and other leaders, and driving IP delivery in a hybrid onsite/offsite environment.

The position requires 8+ years in security or chip industries, deep SoC/IP/FPGA design knowledge, and strong communication and documentation skills.

Qualifications

• Eight or more years of experience in the security or chip industry in R&D centers or system laboratories.
• In-depth knowledge of SoC, Silicon IP and/or FPGA logic design flows.
• In-depth knowledge of hardware description languages (Verilog, VHDL, SystemVerilog) and scripting languages.
• Strong written and verbal communication skills; ability to explain complex concepts to a technical audience.
• Good documentation skills, both in text and drawings.

Responsibilities

• Lead other digital designers, manage projects, estimate cost (effort).
• Design block specification, documentation, and drive IP architecture; encourage innovative ideas and patents.
• RTL design, lint, CDC analysis, synthesis, IP release.
• Work with verification team on planning, simulations, debugging, formal verification, and technical reviews.
• Contribute to flow and methodology development within the R&D group and guide Rambus' technical direction.
• Interact with technical leaders across engineering, product management, sales and FAE teams to ensure high-value product development.

Skills

Embedded hardware development

Cryptography & security

Verilog/VHDL/SystemVerilog

Scripting languages

Communication skills

Documentation skills

Education

BS or MS in Hardware Engineering or Computing Science

Job description

Rambus, a premier chip and silicon IP provider, seeks a Lead Member of Technical Staff Logic Design Engineer to join our Silicon IP team in Vught. The role involves leading digital design for secure IPs, coordinating with verification, architecture and other leaders, and driving IP delivery in a hybrid onsite/offsite environment.

The position requires 8+ years in security or chip industries, deep SoC/IP/FPGA design knowledge, and strong communication and documentation skills.