Graduate FPGA Engineer - Trainee for Low-Latency Hardware

ittihad medical centre; Amsterdam; On-site; EUR 42,000 - 54,000; Full time

Job summary

IMC is seeking a Graduate Hardware Engineer to join a five-week Global Trainee Programme led by experienced engineers. You’ll work with graduates across Europe, the US, and Asia-Pacific to build real-world, high-impact FPGA projects.

After the programme, you’ll continue development with a mentor, applying lessons to low-latency trading systems. Start options are February or August 2027.

Qualifications

• Recently graduated or graduating by 2027 with a STEM degree.
• Experience with HDL languages VHDL/Verilog/SystemVerilog.
• Proficiency in C++ or Python.
• Strong analytical and problem-solving abilities.
• Collaborative mindset and teamwork.
• Interest in how tech shapes financial markets; no prior finance required.
• Available to start full-time in February or August 2027.

Responsibilities

• Design, implement, and validate improvements to IMC's FPGA trading systems.
• Work hands-on with hardware and development tools to optimise performance.
• Participate in pair programming, code reviews, and design discussions.
• Collaborate with traders and software engineers on low-latency systems.
• Grow through workshops, training sessions, and networking with engineers.

Skills

VHDL/Verilog

C++

Python

Analytical thinking

Team collaboration

Interest in tech & markets

Education

Bachelor's degree in Computer Science

Bachelor's degree in Software Engineering

Bachelor's degree in Electrical Engineering

Related discipline

Tools

VHDL

Verilog

SystemVerilog

Job description

IMC is seeking a Graduate Hardware Engineer to join a five-week Global Trainee Programme led by experienced engineers. You’ll work with graduates across Europe, the US, and Asia-Pacific to build real-world, high-impact FPGA projects.

After the programme, you’ll continue development with a mentor, applying lessons to low-latency trading systems. Start options are February or August 2027.