FPGA Hardware Engineer Intern - Hands-on Mentorship

IMC Trading; Amsterdam; On-site; EUR 11,000 - 20,000; Full time

Benefits offered by this job

Fully furnished accommodation

Catered meals

Competitive pay

Job summary

IMC Trading in Amsterdam invites you to join its internship programme as a Hardware Engineer Intern. You’ll contribute to FPGA development, pair programming, and meaningful hardware changes within a fast‑paced, collaborative trading and tech environment.

The internship offers dedicated mentors, workshops, and fully supported living arrangements with meals. Penultimate year students in CS/SE/EE graduating in 2028, with VHDL/Verilog/SystemVerilog and C++ or Python, are encouraged to apply.

Qualifications

• Penultimate year CS/SE/EE, graduating in 2028.
• Familiar with hardware description languages: VHDL/Verilog/SystemVerilog; C++ or Python preferred.
• Thrives in a creative, collaborative, and innovative environment.
• Desire to impact meaningful, challenging projects.
• Strong analytical skills; able to solve problems programmatically.
• Genuine interest in financial markets; prior knowledge not required.
• Internship length: 3–6 months, Apr–Sep 2027.

Responsibilities

• Enhance knowledge of FPGAs by working with the latest technology and writing fluent code.
• Participate in regular pair programming and peer reviews.
• Contribute to hardware change identification, implementation, and validation at IMC.
• Attend workshops, trainings, and social activities with the internship cohort.

Skills

FPGA development

VHDL

Verilog

SystemVerilog

C++

Python

Team collaboration

Analytical thinking

Education

Penultimate year CS/SE/EE (graduating 2028)

Job description

IMC Trading in Amsterdam invites you to join its internship programme as a Hardware Engineer Intern. You’ll contribute to FPGA development, pair programming, and meaningful hardware changes within a fast‑paced, collaborative trading and tech environment.

The internship offers dedicated mentors, workshops, and fully supported living arrangements with meals. Penultimate year students in CS/SE/EE graduating in 2028, with VHDL/Verilog/SystemVerilog and C++ or Python, are encouraged to apply.