Staff IP Design Engineer

Lattice Semiconductor; George Town; On-site; MYR 120,000 - 180,000; Full time

Job summary

Lattice Semiconductor is seeking a qualified candidate in George Town, Penang, for a role focused on the design and development of Lattice Foundation IP. The successful applicant will lead safety qualification research and collaborate closely with cross-functional teams to manage the IP release cycle.

Candidates should hold a Bachelor’s or Master’s degree in relevant fields, boasting over 8 years of experience in SoC and FPGA development. Responsibilities include aligning product features with safety requirements and conducting thorough testing and validation.

Qualifications

• 8+ years of experience in SoC and/or FPGA IP development.
• Hands-on experience in FPGA RTL design and logic verification.
• Ability to generate audit-ready Functional Safety evidence.

Responsibilities

• Lead research and design of safety qualification for Foundation IP.
• Work with cross-functional teams on Lattice Foundation IP release.
• Conduct safety impact assessment, development, testing, and validation.

Skills

Strong communication skills

FPGA architecture knowledge

SoC and/or FPGA RTL design

Education

Bachelor's or Master's in Computer Science, Computer Engineering, Electrical Engineering

Tools

FPGA software tools

Job description

Job Description

A successful candidate will join a team designing and developing Lattice Foundation IP at Penang to help establish long‑term capability in IP‑level Functional Safety readiness and product robustness. The candidate will lead research, design and development of safety qualification of Foundation IP and or safety‑relevant aspects of FPGA EDA design flow, ensuring alignment with product, quality and Functional Safety requirements. The candidate is expected to work closely with cross‑functional teams to plan and execute Lattice Foundation IP release cycle including requirement analysis, feature scoping, safety impact assessment, development, testing, validation and release sign‑off.

Requirements & Skills

• Bachelors, Masters or better in Computer Science, Computer Engineering, Electrical Engineering, or related fields with 8+ years of experience in SoC and/or FPGA IP development.

Experience

• Strong communication skills.
• Knowledge or experience in FPGA architecture and FPGA software tools, specifically for device modeling and soft IP development.
• Hands‑on experience in SoC and/or FPGA RTL design, testbench development, logic verification, timing closure and debugging in accordance with functional safety requirements.

Preferred

• Demonstrate technical ownership of safety related SoC and or FPGA Soft IP development and verification with proven ability to generate audit‑ready Functional Safety evidence in compliance with IEC 61508, ISO 26262 or other safety standards.
• Working knowledge of any FPGA primitives such as embedded block RAM, DSP blocks, PLL, oscillators, I/O Gearing, configuration/security or power related silicon features is a plus.

Behaviors/Motivations

• Technical leadership: Serves as a recognized technical leader who influences cross‑organization engineering decisions/efforts.
• Accountability: Owns outcomes spanning multiple projects or releases, balancing short term delivery with long term technical health.
• Execution: Anticipates organizational and technical risks and drives alignment across teams to resolve them.
• Mentorship: Creates leverage by mentoring engineers, setting technical direction, and establishing best practices adopted broadly.

Additional Information

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

Malaysia

Applications are welcome from all qualified candidates.