Staff Engineer, Signal Test Leader

Celestica Inc.; Penang; On-site; MYR 150,000 - 210,000; Full time

Job summary

Celestica Inc. in Penang seeks a Staff Engineer, Signal Test Leader to own signal and power integrity test planning, unify project test plans, and drive lab activities. You will interact with customers and internal teams, leading debugging and failure analysis while mentoring junior engineers.

The role requires 8–10 years in hardware testing, with deep expertise in PCIe, CXL, DDR5, and related interfaces, plus strong leadership and communication skills.

Qualifications

• Minimum 8–10 years in hardware board-level testing with leadership responsibilities.
• Degree in Electrical Engineering or equivalent.
• Strong lab management and customer-facing collaboration experience.

Responsibilities

• Develop and approve comprehensive SI/PI test plans with scope, schedule, and resources.
• Create a unified Master Test Plan for each project.
• Drive project milestones and manage lab bench scheduling.
• Interface with customers, TPLs, and hardware teams; lead debugging and FA sessions.
• Perform final project-level data reviews to ensure quality before release.
• Establish SOPs and templates to shorten testing times and broaden coverage.
• Mentor engineers on advanced equipment usage and automation (Python/SCPI).

Skills

Signal Integrity

Power Integrity

Lab management

Python/SCPI

Troubleshooting

Leadership

Customer interface

Education

Electrical Engineering degree

Tools

Oscilloscopes

Vector Network Analyzers (VNA)

BERTs

TDR

Active probes

Job description

Staff Engineer, Signal Test Leader

Date: Jul 8, 2026

Location: Penang, 07, MY

Responsibilities and Qualifications

• Validation Planning & Ownership: Develop and approve comprehensive Signal Integrity (SI) and Power Integrity (PI) test plans, defining scope, schedule estimations, and resource allocations.
• Unified Master Test Plan (MTP): Aggregate technically approved test plan drafts from various engineering pillars into a single, unified Master Test Plan for each project.
• Project & Lab Management: Drive project milestones, manage lab bench scheduling, and dynamically adjust testing timelines based on problem occurrence and troubleshooting.
• R&D & Stakeholder Interface: Act as the primary technical interface for customers, Technical Project Leads (TPLs), and Hardware EE/R&D teams. Lead collaborative debugging, failure analysis (FA), and problem‑solving sessions.
• Quality Assurance & Review: Perform the final "Project‑Level Review" to ensure the complete data package meets rigorous quality standards, and technically approve the data before release.
• Technical Governance: As a Domain Champion, establish and maintain "Master Technical Templates" and Standard Operating Procedures (SOPs) to shorten testing times and broaden test coverage.
• Expert‑Level Support & Mentorship: Serve as the Subject Matter Expert (SME) to resolve complex technical roadblocks, bugs, or equipment failures. Mentor and train junior engineers on advanced equipment usage and automation (Python/SCPI).
• Experience: Minimum 8–10 years in hardware board‑level testing, with a clear progression of technical and leadership responsibilities.
• Architectural Expertise (Preferred): In‑depth understanding of PC, server, storage, and communication product architectures from an electrical, SI, and PI perspective.
• Technical Domain Depth: Practical mastery of signal integrity theory and validation of key buses:
  • High‑Speed: PCIe (Gen 5/6/7), CXL, DDR5, SAS/SATA, LAN, and ultra‑high‑speed interfaces (up to 224G).
  • Power Integrity (PI): Power noise, DC‑DC testing, and rail characterization.
  • Low‑Speed/Sideband: I2C, SPI, USB, and SMBus.
  • Clock: Noise Jitter measurement
• Instrumentation Mastery: Expert hands‑on capability with high‑end lab equipment (e.g., high‑bandwidth oscilloscopes, Vector Network Analyzers [VNA], BERTs, TDR, and active probes).
• Leadership: Strong teamwork spirit with proven experience in managing workloads, scheduling, and customer communication.

Physical Demands

• Duties of this position are performed in a normal office environment.
• Duties may require extended periods of sitting and sustained visual concentration on a computer monitor or on numbers and other detailed data.
• Repetitive manual movements (e.g., data entry, using a computer mouse, using a calculator, etc.) are frequently required.
• Occasional travel may be required.

Typical Experience

Minimum 8–10 years in hardware board‑level testing, with a clear progression of technical and leadership responsibilities.

Typical Education

Degree in Electrical Engineering or equivalent.

Celestica is an equal opportunity employer. All qualified applicants will receive consideration for employment and will not be discriminated against on any protected status (including race, religion, national origin, gender, sexual orientation, age, marital status, veteran or disability status or other characteristics protected by law). At Celestica we are committed to fostering an inclusive, accessible environment, where all employees and customers feel valued, respected and supported. Special arrangements can be made for candidates who need it throughout the hiring process. Please indicate your needs and we will work with you to meet them.