Senior SI/PI Engineer – Chip Packaging & Interconnects

Avensys Consulting; Kuala Lumpur; On-site; MYR 180,000 - 260,000; Full time

Benefits offered by this job

Base salary

Company benefits

Career progression

Job summary

Avensys Consulting is seeking a Senior / Staff-level Signal Integrity & Power Integrity Engineer in Kuala Lumpur. The role centers on SI/PI analysis for semiconductor packages, substrates, and high-speed interconnects, with close collaboration to Mandarin-speaking stakeholders and cross-functional teams.

The candidate will analyze DDR, PCIe, Ethernet and SerDes interfaces, develop models (IBIS/IBIS-AMI/S-parameters), and drive package-board co-design activities.

Qualifications

• 5+ years of relevant engineering experience.

Responsibilities

• Perform Signal Integrity (SI) and Power Integrity (PI) analysis for semiconductor packages, substrates, boards, and high-speed interconnects.
• Support package design and package-board / chip-package-board co-design activities.
• Analyze high-speed interfaces including DDR, PCIe, Ethernet, SerDes, and other high-speed I/O technologies.
• Conduct eye diagram and jitter analysis, crosstalk assessment, impedance discontinuity analysis, and signal loss evaluation.
• Perform Power Delivery Network (PDN) and Power Integrity analysis to identify and resolve power delivery issues.
• Develop and use simulation models including IBIS, IBIS-AMI, and S-parameters for channel and system-level analysis.
• Perform S-parameter extraction and channel simulation/modeling for high-speed interconnects.
• Collaborate with package, substrate, board, architecture, design, and validation teams to identify design risks and drive solutions.
• Communicate technical findings, recommendations, and design trade-offs to engineering stakeholders and Mandarin-speaking teams.

Skills

Mandarin language

Tools

Ansys HFSS

Ansys SIwave

Cadence Sigrity

Keysight ADS

HyperLynx

Job description

Avensys Consulting is seeking a Senior / Staff-level Signal Integrity & Power Integrity Engineer in Kuala Lumpur. The role centers on SI/PI analysis for semiconductor packages, substrates, and high-speed interconnects, with close collaboration to Mandarin-speaking stakeholders and cross-functional teams.

The candidate will analyze DDR, PCIe, Ethernet and SerDes interfaces, develop models (IBIS/IBIS-AMI/S-parameters), and drive package-board co-design activities.