Senior FPGA RTL and Firmware Development Engineer

altera; Seberang Perai; On-site; MYR 120,000 - 180,000; Full time

Job summary

Altera is seeking an experienced FPGA RTL and Firmware Development Engineer to join the Platform Hardware Board Engineering team. This hands-on role demands 10+ years of FPGA RTL design and practical firmware capability for platform solutions and development kits.

The candidate will work with FPGA architecture, board design, silicon, software, and Altera kit teams to deliver robust validation boards and platform enablement for next-gen Altera FPGA devices.

Qualifications

• 10+ years of FPGA RTL design, implementation, and system-level validation.
• Strong hands-on experience with Verilog and/or VHDL and digital logic design.
• Experience with Nios II soft-core and embedded firmware in C/C++.
• Ability to work across global cross-functional teams.
• Familiarity with Altera Quartus II and EDS toolchains.
• Ability to bring up and debug FPGA development boards.

Responsibilities

• Define, architect, design, implement, and validate FPGA RTL solutions for platform hardware and development kits.
• Lead the FPGA development flow from planning to timing closure and release readiness.
• Develop embedded firmware for FPGA-based systems using the Nios II core.
• Utilize the Altera EDS and Quartus II flow to build, debug, and validate software components.
• Translate requirements into scalable RTL, firmware interfaces, and verification plans.
• Support board bring-up, hardware-software integration, and system initialization.
• Plan and execute lab validation, stress testing, and defect investigations.
• Create reusable RTL blocks, firmware components, and diagnostic tools to improve efficiency.
• Collaborate with architecture, board design, silicon, software, and system teams to resolve issues.

Skills

FPGA RTL design

Verilog/VHDL

Embedded firmware

Nios II

Lab debugging

Cross-functional teamwork

Education

Bachelor's degree in EE/CE/CS

Tools

Altera Quartus II

Altera Embedded Design Suite (EDS)

Nios II software tools

Job description

Job Details

Job Description

Position Overview

Altera is seeking an experienced FPGA RTL and Firmware Development Engineer to join the Platform Hardware Board Engineering team. This role is intended for a hands-on technical contributor with 10+ years of FPGA RTL design experience and practical firmware development capability. The engineer will own or lead FPGA-based platform solutions spanning RTL architecture, implementation, embedded firmware, system bring-up, validation, and cross-functional debug.

The successful candidate will work closely with FPGA architecture, board design, silicon engineering, software, and Altera development kit teams to deliver robust development kits, validation boards, and platform-level enablement for next-generation Altera FPGA devices.

What You Will Do

• Define, architect, design, implement, and validate FPGA RTL solutions using Verilog and/or VHDL for platform hardware, development kits, and validation boards.
• Lead the complete FPGA development flow, including design planning, simulation, synthesis, implementation, timing analysis, timing closure, configuration, and release readiness using Altera Quartus II tools.
• Develop and maintain embedded firmware in C and/or C++ for FPGA-based systems, with particular emphasis on the Nios II soft-core processor and associated peripherals.
• Use the Altera Embedded Design Suite (EDS) alongside the Altera Quartus II development flow to build, debug, integrate, and validate Nios II-based embedded applications and software components.
• Translate system, functional, and performance requirements into scalable RTL, register maps, firmware interfaces, and verification strategies.
• Support board bring-up, FPGA configuration, hardware-software integration, system initialization, and feature enablement on development and validation platforms.
• Plan and execute simulation, lab validation, stress testing, interoperability testing, and system-level debug using oscilloscopes, logic analyzers, protocol analyzers, and other laboratory equipment.
• Investigate complex issues across RTL, firmware, FPGA timing, board interfaces, clocking, resets, memory, and peripheral integration; drive root-cause analysis and corrective actions.
• Develop reusable RTL blocks, firmware components, test utilities, diagnostic tools, and automation scripts to improve platform development and validation efficiency.
• Collaborate with architecture, board design, silicon, software, applications, and system engineering teams to resolve technical issues and reduce platform risks.
• Review technical designs, RTL, firmware, verification plans, timing reports, lab data, and issue-tracking records; provide technical guidance to less-experienced engineers.
• Document RTL designs, interfaces, test procedures, debug findings, validation results, and release criteria in accordance with Altera engineering standards.

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline; advanced degree is a plus.
• 10+ years of professional experience in FPGA RTL design, implementation, and system-level validation.
• Strong hands-on experience with Verilog and/or VHDL, digital logic design, computer architecture, clock-domain crossing, reset design, and FPGA-based system integration.
• Proven experience with the Altera Quartus II FPGA development flow, including simulation, synthesis, implementation, timing analysis, timing closure, and device programming.
• Working knowledge of C and/or C++ for embedded firmware, hardware-software integration, diagnostics, or platform validation.
• Experience developing or integrating firmware for the Nios II soft-core processor, including peripheral access, interrupt handling, memory-mapped I/O, drivers, or board-support software.
• Practical experience with the Altera Embedded Design Suite (EDS) for Nios II software development, build, debug, and integration.
• Demonstrated ability to bring up and debug FPGA development boards or complex hardware platforms using lab equipment and structured debug methods.
• Strong analytical, problem-solving, communication, and technical documentation skills.
• Ability to work effectively across global, cross-functional engineering teams and independently drive deliverables to completion.

Preferred Qualifications

• Experience with Nios II system architecture, Platform Designer/Qsys integration, custom IP, Avalon interfaces, DMA, memory controllers, and peripheral subsystems.
• Experience creating RTL-to-firmware interfaces, register specifications, device drivers, diagnostics, and automated validation tools.
• Knowledge of FPGA configuration, boot flows, JTAG, PCIe, Ethernet, DDR memory, high-speed serial interfaces, or other board-level interfaces.
• Familiarity with SystemVerilog, assertion-based verification, or other modern verification techniques.
• Experience with Python, Tcl, or similar scripting languages for build automation, regression