IO Circuit Design Engineer

Silicon One Sdn Bhd; Penang; On-site; MYR 180,000 - 240,000; Full time

Job summary

Jora Malaysia is seeking a senior full-custom design engineer in Penang to define module specifications and oversee design lifecycles from concept to tape-out.

The candidate should have 5+ years in IP/SoC mixed-signal design, strong analog circuit knowledge, and extensive experience with EDA tools like Cadence, Hspice, and Virtuoso. This role emphasizes layout collaboration and verification.

Qualifications

• 5+ years hands-on IP or SoC design experience in mixed-signal IO or system validation.
• Mastery of full-custom design methodologies with standard EDA tools for design and simulation.
• Strong knowledge of analog circuit design, signal integrity, and device characteristics.
• Experience with LVDS, DDR3/4/5, LPDDR4/5, ADC, PLL, or Clock Networks (preferred).

Responsibilities

• Define module specifications and full-custom design tasks
• Support layout activities, including floorplanning and optimization
• Independently oversee and perform module design tasks using full-custom flows based on advanced process nodes
• Work with system designers to refine analog circuit models and optimize design performance
• Lead final layout verification (DRC/LVS) and ensure the integrity of final tape-out data (GDSII)

Job description

Jora Malaysia will close on 9th September 2026. Thank you for being with us, we are cheering you on as you continue your career journey.

This is a full-custom design role focused on mixed-signal IO and system validation. You will define module specifications, lead full-custom design tasks, and oversee the complete design lifecycle from initial specification through to successful tape-out.

Key responsibilities

Define module specifications and full-custom design tasks

Support layout activities, including floorplanning and optimization

Independently oversee and perform module design tasks using full-custom flows based on advanced process nodes

Work with system designers to refine analog circuit models and optimize design performance

Lead final layout verification (DRC/LVS) and ensure the integrity of final tape-out data (GDSII)

About you

Minimum 5+ years of hands‑on experience in IP or SoC design, focusing on mixed-signal IO or system validation

Mastery of full-custom design methodologies and proficiency with standard EDA tools for circuit design and simulation

Strong understanding of analog circuit design, signal integrity, and device characteristics

Proficient with EDA tools: Cadence, Hspice, Virtuoso, Spectre, AMS, etc.

Strong foundation in analog circuit design and signal integrity

Experience in designing LVDS, DDR3/4/5, LPDDR4/5, ADC, PLL, or Clock Networks (preferred)

Bachelor's degree or above (Microelectronics or Integrated Circuits preferred)