Emulation Engineer

UST; Penang; On-site; MYR 67,000 - 134,000; Full time

Job summary

UST in Penang is seeking a hardware verification engineer to contribute to emulation-based functional verification. You will participate in test plan creation, content development, and waveform analysis, leveraging Verilog and emulation models to ensure robust design validation.

The role requires exposure to Python and TCL scripting, with AXI knowledge and PCIe familiarity considered a plus. A bachelor’s degree in EEE or related field is expected.

Qualifications

• Bachelor’s degree or higher in Electrical and Electronics Engineering or a related field.
• Strong knowledge of Verilog and emulation concepts.
• Exposure to scripting languages such as Python and TCL.

Responsibilities

• Involved in emulation-based functional verification including test plan definition and test content development.
• Demonstrate understanding of Verilog, emulation models, and waveform debugs.

Skills

Verilog

Emulation debugging

Python

TCL

AXI knowledge

PCIe knowledge

Education

Bachelor’s degree in Electrical and Electronics Engineering

Tools

Verilog emulation tools

Job description

• Will be Involved in Emulation based functional verification that includes test plan definition, test content development.
• Good understanding in Verilog, emulation models, waveform debugs.
• Exposure to scripting programs like Python, TCL
• Good understanding in Verilog, emulation model compilation, waveform debugs.
• Basic understanding in AXI. Knowledge in PCIE is a plus.
• Bachelor’s degree or higher in Electrical and Electronics Engineering or related field