Circuit Design Engineer

Silicon One; Bayan Lepas; On-site; MYR 120,000 - 180,000; Full time

Benefits offered by this job

Competitive rewards

Full lifecycle exposure

Job summary

Silicon One, based in Bayan Lepas, Penang, Malaysia, is seeking a senior engineer to lead full-custom design tasks and drive IP/SoC development for mixed-signal IO.

The role requires independent design ownership, deep analog fundamentals, and proficiency with leading EDA tools to deliver tape-out-ready layouts and validated layouts with DRC/LVS checks.

Qualifications

• Minimum 5+ years hands-on IP/SoC design experience in mixed-signal IO or system validation.

Responsibilities

• Design & Architecture: Define module specifications and lead full-custom design tasks.

Skills

5+ years IP/SoC design

Full-custom design

Mixed-signal IO

Analog circuit design

Signal integrity

Mandarin language advantage

Education

Bachelor's degree or above in Microelectronics or ICs

Tools

Cadence

HSPICE

Virtuoso

Spectre

AMS

Job description

Jora Malaysia will close on 9th September 2026. Thank you for being with us, we are cheering you on as you continue your career journey.

• Design & Architecture: Define module specifications and lead full-custom design tasks.
• Physical Implementation: Support layout activities, including floorplanning and optimization.
• Full-Custom Design: Independently oversee and perform module design tasks using full-custom flows based on advanced process nodes.
• Collaboration: Work with system designers to refine analog circuit models and optimize design performance.
• Tape-out Delivery: Lead final layout verification (DRC/LVS) and ensure the integrity of final tape-out data (GDSII).

Responsibility

Location: Bayan Lepas, Penang, Malaysia

Job Type: Full-time (On-site)

Key Responsibilities

Requirements

• Design & Architecture: Define module specifications and lead full-custom design tasks.
• Physical Implementation: Support layout activities, including floorplanning and optimization.
• Full-Custom Design: Independently oversee and perform module design tasks using full-custom flows based on advanced process nodes.
• Collaboration: Work with system designers to refine analog circuit models and optimize design performance.
• Tape-out Delivery: Lead final layout verification (DRC/LVS) and ensure the integrity of final tape-out data (GDSII).

Position Requirements

• Experience: Minimum 5+ years of hands-on experience in IP or SoC design, focusing on mixed-signal IO or system validation.
• Experience: Extensive hands-on experience in IP or SoC design, specifically in mixed-signal IO or system validation.
• Technical Skills: Mastery of full-custom design methodologies and proficiency with standard EDA tools for circuit design and simulation. Strong understanding of analog circuit design, signal integrity, and device characteristics.
• Proficient with EDA tools: Cadence, Hspice, Virtuoso, Spectre, AMS, etc.
• Strong foundation in analog circuit design and signal integrity.
• Preferred Domains: Experience in designing LVDS, DDR3/4/5, LPDDR4/5, ADC, PLL, or Clock Networks.
• Language & Communication: Excellent communication skills. Ability to speak and write in Mandarin is a significant advantage.
• Education: Bachelor's degree or above (Microelectronics or Integrated Circuits preferred).

Why Silicon One?

• Full Lifecycle Exposure: Drive designs from initial specification through to successful tape-out.
• Competitive Rewards: We offer a highly attractive compensation package for top-tier lead talent.