Physical Design Engineer

North American Production Sharing de México, S.A. de C.V.; Tijuana; Presencial; MXN 600,000 - 800,000; Jornada completa

Descripción de la vacante

A leading technology firm in Tijuana is seeking an experienced ASIC Engineer to work on innovative chip design and development. The role demands collaboration with cross-functional teams and responsibilities include managing the Physical Design Flow of complex, high‑speed, low‑power designs. A Bachelor's or Master's degree in Engineering is required, along with experience in Physical Design and associated tools such as Cadence Innovus and Synopsys Fusion Compiler.

Responsabilidades

• Responsible for the complete Physical Design Flow and deliveries of complex designs.
• Develop and enable low‑power implementation methods.
• Debug timing violations and fix physical violations.

Conocimientos

Physical Design

Place & Route tool experience

Timing closure experience

Formal verification

Power domain analysis

Physical verification

Educación

Bachelor's / Masters degree in Science, Engineering, or related field

Herramientas

Cadence Innovus

Synopsys Fusion Compiler

Synopsys PTSI

Descripción del empleo

Overview

As a leading technology innovator, we push the boundaries of what's possible to enable next‑generation experiences and drive communication and data processing transformation to help create a smarter, connected future for all. As an ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world‑class products. Engineers collaborate with cross‑functional groups to determine product execution path.

Digital ASIC Team is actively seeking candidates for several physical design engineering positions in our SOC and core design team. As a physical design engineer you will innovate, develop, and implement chips and cores using state‑of‑the‑art tools and technologies.

Responsibilities

You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high‑speed, low‑power designs such as GPU, Camera and other MM, DDR, Modem, Audio. Tasks also involve the development and enablement of low‑power implementation methods, customized P&R to achieve area reduction, performance, and power goals. Additional responsibilities in this role involve good understanding of functional and test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, cell placement, multi‑mode & multi‑corner (MMMC) clock‑tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross‑talk noise and delay analysis, debugging timing violations for MMMC designs, implementing timing fixes and functional ECOs, debugging and fixing physical violations, and formal verification. The individual also should have deep knowledge on scripting and software languages including Python, PERL/TCL, Linux/Unix shell and C. This individual will design, verify, and deliver complex Physical Design solutions from netlist and timing constraints to the final product.

Qualifications

• Bachelor's / Masters degree in Science, Engineering, or related field

Preferred Qualifications

• 2+ years industry experience/coursework in the following areas:
• Physical Design
• Place & Route tool experience on Cadence Innovus and/or Synopsys Fusion Compiler
• Timing closure experience in Synopsys PTSI
• Formal verification experience
• Power domain analysis experience
• Physical verification experience