DFT Engineer

QUALCOMM, Inc.; Tijuana; Presencial; MXN 420.000 - 660.000; Jornada completa

Descripción de la vacante

QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA seeks engineers to implement and verify advanced DFT/DFD techniques for low-power, multi-voltage ASIC designs. You will contribute to reducing test costs, increasing product quality, and improving yield learning on cutting-edge process tech.

The role focuses on DFT pattern generation, coverage analysis, and debugging, plus running and debugging gate-level simulations. Prior DFT experience with scan and MBIST is valued.

Formación

• Bachelor's degree in Science, Engineering, or related field with 2+ years in ASIC design/verification.
• Experience with advanced DFT/DFD techniques for low power and multi voltage designs.
• Knowledge of core-based test methodology and scan isolation.

Responsabilidades

• DFT pattern generation, coverage analysis and debug.
• Run and debug gate-level simulations for DFT/DFD.
• Contribute to pre- and post-silicon DFT activities.

Conocimientos

DFT/DFD techniques

Scan/ATPG

MBIST

JTAG

Gate-level simulation

Test coverage analysis

Educación

Bachelor's degree in Science/Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Herramientas

EDA ATPG tools

Scan/Insertion tools

Descripción del empleo

Company:

QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.

The Digital ASIC Design Team is currently seeking candidates who will be responsible for the implementation and verification of advanced DFT/DFD (Design for Test/Design for Debug) techniques for low power, multi voltage designs. The successful candidate will help in the deployment of DFT methodologies that reduce test cost, increase product quality, and enhance yield learning on leading edge process technologies. The candidate should have solid hands-on experience with industry standard DFT techniques such as scan and MBIST. Job responsibilities include DFT pattern generation, coverage analysis and debug as well as running and debugging gate level simulations. The ideal candidate will have experience in both pre, and post-silicon in the DFT domain.

Preferred Qualifications

• * 3+ years industry experience in the implementation and verification of advanced DFT/DFD (Design for Test/Design for Debug) techniques for low power and multi voltage domain designs. A strong fundamental knowledge of DFT is required
• * Understanding of core-based test methodology and scan isolation.
• * Knowledge of various fault models such as Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, and Cell Aware.
• * Knowledge in JTAG, Scan Compression, ATPG, Fault Simulation and at-speed testing.
• * Experience with industry EDA ATPG and insertion tools.
• * Experience in DFT implementation, Scan/ATPG, MBIST insertion/validation, coverage analysis.

Minimum Qualifications:

• • Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
• ORMaster's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
• ORPhD in Science, Engineering, or related field.

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