Analog IC Layout Engineer

The Adecco Group; Región Centro; Hybrid; MXN 420,000 - 620,000; Full time

Benefits offered by this job

Social Insurance (IMSS)

12 Vacation days per year

15 Days of Christmas Bonus

25 % Vacation Bonus

Life Insurance

Hybrid Work (Tue–Thu onsite)

Job summary

The Adecco Group in Mexico is seeking an experienced analog/mixed-signal IC layout engineer to design, floorplan, and route layouts for high-volume production silicon. You will collaborate with circuit designers through tape-out in a hybrid onsite setup.

Requirements include 3+ years in analog/mixed-signal IC layout, Cadence Virtuoso, and strong English. Familiarity with Calibre/PVS and submicron process effects is preferred; join a supportive team with growth opportunities.

Qualifications

• +3 years of hands-on experience in analog or mixed-signal IC layout.
• Advanced English proficiency.
• Working knowledge of Cadence Virtuoso Layout Editor or equivalent full-custom layout tools.
• Familiarity with Calibre or PVS verification flows (DRC, LVS, ERC).
• Understanding of submicron process effects and layout matching techniques.

Responsibilities

• Design and implement analog layout for cell and block-level IP.
• Floorplan and place devices to meet area, matching, and performance targets.
• Route power and sensitive analog signals.
• Run and resolve DRC/LVS checks.
• Collaborate with circuit designers and verification engineers through to tape-out.

Skills

English - Advanced

Education

Bachelor’s Degree in Information Technologies

Tools

Cadence Virtuoso Layout Editor

Calibre

PVS verification flows

Job description

• Education: Bachelor’s Degree in Information Technologies or related.
• Languages: High level of proficiency in English (speaking, reading, writing) Level: B2, C1, C2,
• Modality: Hybrid Work (Tuesday to Thursday onsite)
• Hiring: 100 % Payroll
• Benefits: Social Insurance (IMSS), 12 Vacation days per year, 15 Days of Christmas Bonus, 25 % Vacation Bonus, Life Insurance.

A hands-on, custom analog layout role, working on production silicon from initial floorplanning through to tape-out, on live, high-volume programs.

Day-to-Day Responsibilities

• Design and implement analog layout for cell and block-level IP
• Floorplan and place devices to meet area, matching, and performance targets
• Route power and sensitive analog signals
• Run and resolve DRC/LVS checks
• Collaborate with circuit designers and verification engineers through to tape-out

Requirements

• +3 years of hands-on experience in analog or mixed-signal IC layout
• Advanced English
• Working knowledge of Cadence Virtuoso Layout Editor, or equivalent full-custom layout tools
• Familiarity with Calibre or PVS verification flows (DRC, LVS, ERC)
• Understanding of submicron process effects (STI, WPE, DFM) and layout matching techniques
• Comfortable working in a hybrid onsite environment, collaborating directly with the local and wider design team.